th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA 2013) Suzhou, China July 2013

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1 th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA 2013) Suzhou, China July 2013 IEEE Catalog Number: ISBN: CFP13777-POD

2 TABLE OF CONTENTS Development And Application Of Prognostics And Health Management Technology... 3 S. Xie, Y. En, X. Lin, Y. Lu, Y. Chen Eliminating The Top Causes Of Customer-Attributable Integrated Circuit Failures... 8 A. Olney Ultra High Precision Circuit Diagnosis Through Seebeck Generation And Charge Monitoring C. Boit, C. Helfmeier, D. Nedospasov, A. Fox Building The Electrical Model Of The Pulsed Photoelectric Laser Stimulation Of A PMOS Transistor In 90nm Technology A. Sarafianos, O. Gagliano, M. Lisart, V. Serradeil, J. Dutertre, A. Tria Optical Probing Of FinFETs J. Fine, C. Young, C. Hobbs, G. Bersuker, T. Lundquist, C. Tsao Thickness Measurement Of Si Substrate With Infrared Laser Of Optical Beam Induced Resistor Change (OBIRCH) In Failure Analysis L. Tian, M. Wu, D. Fan, C. Wu, G. Wen, D. Wang A Non Destructive Scan Diagnosis Based Fault Isolation Technique Verification Method Using Infrared Laser Stimulation On Wafer Level G. You, S. Goh, B. Yeoh, H. Hu, N. Chung, T. Fei, C. Yap, T. Lim, J. Lam Bias-Temperature Instability Of Si And Si(Ge)-Channel Sub-1nm EOT p-mos Devices: Challenges And Solutions G. Groeseneken, M. Aoulaiche, M. Cho, J. Franco, B. Kaczer, T. Kauerauf, J. Mitard, L. Ragnarsson, P. Roussel, M. Toledano-Luque Understanding Correlated Drain And Gate Current Fluctuations W. Goes, M. Toledano-Luque, O. Baumgartner, M. Bina, F. Schanovsky, B. Kaczer, T. Grasser Impact Of Cerium Oxide's Grain Size For Dielectric Relaxation C. Zhao, M. Werner, S. Taylor, P. Chalker, P. King Investigation Of Chromium Contamination Induced TDDB Degradation In MOSFET C. Hsiao, A. Teng, W. Chang, Y. Chen, M. Lee, Y. Tsai, T. Lee, D. Lin, A. Dai, C. Lu Failure Analysis Considerations In Designing For EOS/ESD Robustness J. Hajjar, A. Righter, E. Wolfe, A. Olney A. High Latchup - Immune ESD Protection SCR-Incorporated BJT In Deep Submicron Technology C. Huang, F. Chiu, J. Chi, Y. Huang, Q. Chen, J. Tseng A Study Of Latch-Up Mechanisms For Adjacent Pins On Multiple Power Supply Circuits S. Liang, A. Guo, J. Ji, J. Chen, J. Su, J. Wang, J. Wu, J. Lin Application Of Photoemission Microscopy (PEM) And Computer Aided Design (CAD) Navigation System In Localization Of High Side Power Switch Open Contact Failure L. Sern Failure Analysis Of Complicated Case By Functional OBIRCH Method D. Fan, L. Tian, M. Wu, C. Wu, W. Wang, G. Wen Design Flow And Techniques For Fault-Tolerant ASIC Z. Stamenkovic, V. Petrovic, G. Schoof Optimization Of TEM Sample Preparation Methods By FIB For The Increase Of Throughput S. Duan, R. Qi, M. Li, Y. Zhao, L. Chen, Q. Yu, A. Guo, V. Chang, J. Wu, K. Chien Application Of PVC To Significantly Improve The Success Rate In Locating Trench Defect Using FIB After Electrical Failure Localization N. Zakaria Investigation Of Time Domain Reflectometry (TDR) On Power Mosfet Semiconductor Device K. Ng, C. Sin Fast 3D Tomography At Package Level By Using Xe Plasma Focused Ion Beam T. Hrncir, L. Hladik, M. Zadrazil Optical Probing (EOFM / TRI): A Large Set Of Complementary Applications For Ultimate VLSI P. Perdu, G. Bascoul, S. Chef, G. Celi, K. Sanchez Advanced Transient Thermoreflectance 2D Imaging For Integrated Circuit Sub-Micron Defect Detection And Thermal Analysis K. Yazawa, D. Kendig, Y. Zhang, K. Yazawa, A. Shakouri Innovative Way Of Implementing Active Voltage Contrastq A. Sabate, N. Ismail, N. Nordin

3 New Statistical Post Processing Approach For Precise Fault And Defect Localization In TRI Database Acquired On Complex VLSI S. Chef, P. Perdu, G. Bascoul, S. Jacquir, K. Sanchez, S. Binczak New Technique Of Sample Preparation For 3DIC Micro Bumps Observation C. Huang, H. Long, K. Chiang, L. Chuang, K. Tsui Interconnect Reliability Assurance For Circuits With Billions Of Transistors T. Turner A Microwave Plasma Dry Etch Technique For Failure Analysis Of Cu And PdCu Wire Bonds Strength Y. Tan, M. Ng, J. Khoo, C. Tan, C. Silva, K. Sim Composition Distribution Studies Of Sn/Ag/Cu Solder Material Using TOF-SIMS, XPS And EDX H. Lee, Z. Xing, D. Gui, M. Hao, J. Shao, B. Khoo, Y. Shen, X. Li Novel Approach In Selective Area Chemical Etching Of Copper Metallization For Electrical Failure Analysis L. Chuan, N. Zakaria, M. Stephan Uniform Delayering Of Copper Metallization Y. Siah, Y. Hong, Q. Liu, H. Kor, C. Gan The Variability Issues In Small Scale Trigate CMOS Devices: Random Dopant And Trap Induced Fluctuations S. Chung Failure Analysis On Non-Visible Front-End Defects In Deep NWELL Implantation Related Process A. Boon, C. Changqing, Z. Ping, N. Ping, Y. Hong, L. Khim, N. Peng, A. Teo, N. Tiong N-Type Dopant Out Diffusion Induced EEPROM Failure L. Tan, G. Chan, W. Kho, X. Wang Study On Light Sensitive Functional Failures In VLSI Failure Analysis G. Wen, D. Fan, L. Tian, C. Wu, M. Wu, W. Wang Failure Analysis Approach For TrenchMOS Devices O. Khiam, Y. Yujin, A. Gao, L. Yan, L. Khim, L. Keat, K. Mingchu Thin Silicon Wafer Processing And Strength Characterization J. Gambino Electrical Properties Of Low-K Dielectric In Copper Interconnect Structures M. Lin, J. Liang, A. Juan, K. Su Stress Evolution On Tungsten Thin-Film Of An Open Through Silicon Via Technology A. Singulani, H. Ceric, E. Langer A Correlation Study Of MOL Electrical Test Method With Its Physical Analysis T. Cahyadi, F. Chen, H. Jiang, S. Mittl, E. Chua Reliability Comparison On Self-Aligned Via And Punch-Through Via Etch Methods Of Hard-Mask Based Cu/Ultra Low-K Interconnects J. Zhou, Z. Gan, M. Hu, F. Bai, L. Zhou Charge Pumping In Floating-Body SOI FinFETs D. Fleetwood, E. Zhang Benefits Of Dopant Profile Approach Using Spreading Resistance Profiling L. Sing, L. Ping A Sample Preparation Technique To Reveal The Implant Profile By TEM For IC Failure Analysis M. Li, W. Chien, S. Duan Strain Measurement Of Fin Structure Using TEM Objective Lens Dark-Field Off-Axis Holography J. Zhu, H. Tan, A. Bello, D. Pham, Y. Zhou, B. Liu, Z. Mai, A. Du, S. Zhao Reliability Of AlGaN/GaN HEMTs: Permanent Leakage Current Increase And Output Current Drop D. Marcon, J. Viaene, P. Favia, H. Bender, X. Kang, S. Lenci, S. Stoffels, S. Decoutere Modelling Of LED Light Source Reliability G. Tao Reliability Evaluation And Failure Analysis Of AlGaN/GaN High Electron Mobility Transistor By Photo Emission Microscope Y. Wang, X. Hong, C. Zeng, P. Lai, Y. Huang Transverse Domain Wall Formation In A Free Layer: A Mechanism For Switching Failure In A MTJ-Based STT-MRAM A. Makarov, V. Sverdlov, S. Selberherr Recent Advances In Fault Isolation For Semiconductor Industry J. Chin, V. Narang, M. Tay, S. Phoa, R. Venkat, L. Ei, S. Lim, C. Teo, S. Zulkifli, W. Qiu, J. Tan, G. Ranganathan, Z. Oh, F. Foo

4 Capacitor Dielectric Defect Or Damage Localization By Photon Emission Microscopy With The Combination Of OBIRCH C. Wu, S. Yao, G. Song, G. Wen, L. Tian, M. Wu, D. Fan Die Front-End Defect Isolation Case Study Using A Combination Of Atomic Force Probing And SEM High Beam Inspection Techniques L. Yin, C. Keng, B. Nan, C. Meng, G. Tan Failure Analysis Based On Dummy TIVA Spot C. Chen, G. Ang, S. Zhao, H. Ng, S. Loh, K. Yip Analysis Of Satellite Defects Formed In Photolithography Process By TOF-SIMS And XPS L. Zhu, H. Teo, Y. Hua, H. Loh, C. Leong, C. Kam, S. Zhao, S. Redkar Trends And Challenges In Solid State Lighting Reliability G. Tao Failure Analysis For Probe Mark Induced Galvanic Corrosion And Bond Degradation During HAST L. Yeoh, K. Chong, S. Li Identification Of Mega Electron Volt Arcing Mechanism Through Detail Microscopic Analysis Approach Y. Khong, H. Leng, L. Sing A Study On The Relationship Between Pad Surface Fluorine Concentration And The Formation Of Pad Corrosion Defect M. Li, W. Chien, Q. Yu, J. Qi Real-Time Analysis Of Ultra-Thin Gate Dielectric Breakdown And Recovery A Reality K. Pey, N. Raghavan, W. Liu, X. Wu, K. Shubhakar, M. Bosman Non-Destructive Open Fault Isolation In Flip-Chip Devices With Space-Domain Reflectometry W. Qiu, S. Tan, M. Tay, J. Gaudestad, V. Talanov, M. Wei Nondestructive Analysis Solution Using Combination Of Lock-In Thermography(LIT) And 3D Oblique X-Ray CT Technology N. Seimiya Factors That Affect Hotspot Localization In Infrared Lock-In Thermography T. Hoe, S. Tan, K. Ng High Resolution Magnetic Current Imaging For Die Level Short Localizationq J. Gaudestad, N. Gagliolo, V. Talanov Design Of Prognostic Circuit For Electromigration Failure Of Integrated Circuit Y. Chen, B. Wang, Y. Zhang, Y. En, Y. Huang, Y. Lu, X. Liu, X. Wang Divide And Conquer Algorithm For Parallel Reconfiguration Of VLSI Array With Faults M. Zhou, J. Wu, G. Jiang, X. Wang, J. Sun Failure Rate Calculation For NMOS Devices Under Multiple Failure Mechanisms Z. Zhou, X. Liu, Q. Shi, Y. En, X. Wang An Unique Method To Fabricate On-Chip Capacitors For Chip-Level EMC Evaluation S. Chen, V. Siao Reliability Of Oxide TFT For Display Application J. Jang, J. Um, M. Mativenga Low Frequency Noise In Polycrystalline p-β-fesi 2 /Ge Heterojunction Solar Cells A. Bag, C. Mukherjee, S. Mallik, C. Maiti Dynamic HC-Induced Degradation In n-type Poly-Si Thin Film Transistors Under Off-State Gate Pulse Voltage H. Wang, M. Wang, M. Zhang Electrical Properties Of N-Type CdS And P-Type CdTe Thin Films In CdS/CdTe Solar Cells J. Wu, F. Ang, C. Zhao, J. Smith Advanced Methodologies For Atomic-Scale Nanofabrication And Dynamic Characterization X. Wu, L. Sun Application Of TEM For Distinguishing The Primary And Secondary Abrasives Of Undiluted CMP Slurry C. Sun, L. Tai, P. Sharma, Y. Ko, Y. Chen, C. Chu, Y. Hsieh, C. Yang, T. Yew Study Of FIB Milling Induced Damage And Contamination On Ex-Situ Lift-Out TEM Specimen And Methodology To Reduce The Artifacts L. Nan, L. Lung Method To Increase Defect Localization Success Rate On Open Failure By Combining Circuit Layout Analysis With Photon Emission Microscopy L. Siong, A. Chin, C. Ling, P. Keng ISTFA Best Paper: FemtoFarad/TeraOhm Endpoint Detection For Microsurgery Of Integrated Circuit Devices J. Colvin

5 Electrical Fault Localization And Scanning Capacitance Microscopy (SCM) Analysis Methodology On High RDSON Failure Of Smart Power Technology IC Device A. Keow, I. Hashim, L. Sern Failure Analysis Of A 2.5D Stacking Using μ Insert Technology A. Nowodzinski, V. Mandrillon, D. Bouchu, R. Franiatte, H. Boutry, D. Bloch, K. Rousseau, C. Lionel Thermal Effect On Die Warpage During Back-Side Die Polishing Of Flip-Chip BGA Device M. Monjur, R. Mezanur, M. Wei, H. Chong, L. Nasar-Abdat, V. Narang A New Failure Analysis Approach To Predict And Localize Defects And Weakness Areas In Trough- Glass-Vias For A Multifunctional Package Level Camera A. Amrani, M. Bouya, Y. Bouissa, A. Benali, M. Faqir, M. Ghogho A Special Failure Analysis Process To Save Some De-Caped Recovered Cases C. Wu, S. Yao, G. Wen, L. Tian, M. Wu, D. Fan, W. Wang Application Of Atomic Force Microscopy In IC/Discrete Failure Analysis P. Yee, L. Sing Comparative Study Of Different Copper Wire Decapsulation Techniques For Failure Analysis E. Julius, N. Cruz, A. Sabate, S. Estrera Dopant Profiling Using Various FA Techniques L. Way, L. Ping, L. Sing Material Contrast Identification And Compositional Contrast Mapping Using Backscattered Electron Imaging J. Lagar, M. Raborar New Gas Applications Of Backside Circuit Edit For Voiding Spontaneous Damage C. Tsai, Y. Huang, Y. Lu, M. Lin Putting The Die Contour Back - Methods In Advanced Sample Preparation For 3D And Flip-Chip Devices C. Richardson, G. Liechty, C. Smith, M. Karow SIMS Sample Preparation Method For GOX Analysis With Small-Size Polysilicon Patterns L. Zhu, H. Teo, M. Lee, H. Ng, C. Chen, G. Ang, Y. Hua, S. Zhao, S. Redkar Study On A Leaf-Like Bonding Pad Defect R. Qi, S. Duan, M. Li, V. Chang, J. Wu, K. Chien Study On Low Silver Sn-Ag-Cu-P Alloy For Wave Soldering J. Wang, X. Wei, W. Zhu, J. Wu, N. Wu SiGe Profile Inspection By Using Dual Beam FIB System In Physical Failure Analysis S. Liu, Y. Hou, C. Chang, J. Lin A Failure Analysis Technique Using The Nano Electrostatic Field Probe Sensor (NEPS) S. Ito, T. Matsumoto A Novel Methodology For Passive Voltage Contrast Fault Isolation On Ultra Thin Gate Oxide Failure J. Tong, K. Li, E. Gong, Q. Guo A Novel Optical Structure Of Numerical Aperture Increasing Lens (NAIL) For Resolution Improvement In Backside Failure Analysis L. Tian, K. Lan, G. Wen, M. Wu, C. Wu, D. Fan, D. Wang Application Of EMMI Contrast Method In Failure Analysis X. Chen, X. Kuang, G. Xu Application Of Transmission EBSD In Aluminium Metal Layer And GaAs/AlAs Epitaxial Layers Y. Shen, E. Lee, S. Chow, B. Khoo, C. Kon, D. Gui, Z. Xing Backside Dynamic Thermal Laser Signal Injection Microscopy (T-LSIM) Fault Isolation Technique On WLCSP Devices Z. Lau, H. Chan Study Of Abnormal Appearances On The Failed Die By FIB Milling Technology L. Liu, G. Xu, F. Mo Development Of High Resolution Scanning Acoustic Tomograph For Advanced LSI Packages K. Kitami, M. Takada, O. Kikuchi, S. Ohno Electrical Fault Isolation Of Intermittent Frequency-Dependent BRAM Functional Failure Using Fast Frequency Initialized Read-Only Test And Failure Pattern Commonality Analysis Y. Karkeong, C. Fang Evaluation Of Thermal Mapping Analysis Technique For Failure Mechanism Y. Yusof, I. Ahmad, N. Halim FIB Fast Positioning Technology And Its Application X. Lin, X. Zhang In Situ Nanomechanical Measurement Of Cu Nanowires Y. Zhang, C. Zhang, X. Han, Y. Ji, J. Ma, Z. Zhang, L. Heiderhoff

6 Investigation Of EOS Damage Issue Induced By Failure Analysis On Back-End Test Vehicle H. Zhang, K. Liew, R. Lin New Capability Of Laser Ablation In Failure Analysis C. Liew, K. Khoo, L. Tiang, Y. Ng Optimize Design On Quantum Effect Photo-Detector Array Board-Level Packaging Y. Ge, F. Guo, L. Ding Real Time Observation Of Nanoscale Multiple Conductive Filaments In RRAM By Using Advanced In-Situ TEM J. Sun, X. Wu, Q. Liu, M. Liu, L. Sun Development Of Failure Analysis Technique For Temperature Dependent Failures N. Hat, A. Sabate, K. Yusof A Study Of Substrate Damage Issue Caused SRAM Device Soft Failure Y. Shu, C. Chen, C. Chao, S. Gang Case Studied Of Failure Threat Caused By Counterfeit Plastic Encapsulated Microcircuits Y. Wang, X. Kuang, C. Huang, S. Li Corrosion Failure Analysis About Package Box Of Aluminum Silicon Alloy Used For Microwave Module H. Li, Q. Cao, Z. Song ESD Detection Circuit With Reverse-Used RC Network In A 90-nm CMOS Process Z. Yang, H. Liu, S. Wang Failure Analysis Of P-N Junction Degradation By High Temperature Reverse Bias Operating Condition S. Choi, K. Lee Failure Localization Methods For System-On-Chip (SoC) Using Photon Emission Microscopy Y. Chen, H. Chen, X. Zhang, P. Lai Failure Mechanism Of Flip-Chip Circuit Interconnects Induced By Electromigration Y. Lu, B. En, Z. Shi Faulty Failure Analyses G. Mura, M. Vanzi Investigation Of Failures On Dual-Dies Stacked Package Y. Chen, W. Lin, H. Huang, M. Hsiao, C. Ko Pulsing Electrical Over-Stress (EOS) Testing And Its Failure Analysis For Advanced Process Integrated Circuits Y. Tseng, C. Wang, Y. Chang Research On Tin Whisker Growth Of Pure Tin Plating Of Different Lead Substrates B. Zhou, Z. Wan, X. Li, Y. En SCM Application In Localized 2D Dopant Profiling L. Shyuan, K. Siong, L. Sern Study Of Process Influences On The Break Down Limit Of High Voltage Transistors In An Embedded EEPROM CMOS Technology By Using EMMI And Nanoprobing A. Acovic, J. Dreybrodt Successful Failure Analysis Using Fault Diagnosis Tool And Product Characterization Board In BiCMOS Technology Low Yield Investigation R. Liu, A. Chin, S. Hong, L. Wenfeng The Effect Of Pb Contamination On The Solidification Behaviors And Mechanical Properties Of Backward Compatible Solder Joints X. Li, B. Zhou, Y. En, X. He, X. Wei The Example Of Circuit Analysis To Assist 2 nd -Generation Hot Spot For The Failure Localization S. Guo, A. Pan, M. Xu, T. Sun, L. Lai A Novel Analysis Method Of Power Signal For Integrated Circuits Trojan Detection L. Wang, H. Xie, H. Luo Analysis Of Dynamic Retention Characteristics Of NWL Scheme In High Density DRAM M. Lee, H. Kwon, J. Lim, H. Hwang, S. Jang, Y. Roh Critical Factors On The Hermetic Characteristics Of DC/DC Power Module X. Li, X. He, Y. En, Q. Guo Optimal Vth Window In Endurance And Retention Enhancement Of MLC Flash K. Hsien, K. Chao, Y. Chen Reliability Characterization Exploring Extreme Conditions For Chips' Design Optimization T. Chu The Application Of Fault Tree Analysis Method In Electrical Component Y. Chen, X. He, P. Lai

7 The Real-Time Fault Diagnosis Of Electrolytic Filter Capacitors In Switching Mode Power Supply Z. Shi, Y. Lu, T. Ning, M. Li, J. Feng, Z. Zhou Channel Hot-Carrier Degradation Characteristics And Trap Activities Of High-k/Metal Gate nmosfets W. Luo, H. Yang, W. Wang, H. Xu, S. Ren, B. Tang, Z. Tang, J. Xu, J. Yan, C. Zhao, D. Chen, T. Ye Failure Mechanism Of Leakage Induced By Pattern-Dependent Photo Resist Distortion M. Wu, L. Tian, D. Fan, C. Wu, G. Wen HV PMOSFET Vth (Threshold Voltage) Shift Caused By HEIP After HTOL K. Lee, H. Jang, K. Kim, J. Park, L. Byunghoon, U. Seo, B. Kim NBTI Life Time Of A High Voltage PMOS FET J. Jia, F. Xue, P. Liu, J. Tien, A. Cai Radiation Response Analyzer Of Semiconductor Dies M. Yifei, Z. Cezhou, S. Shengmao, Z. Yue, I. Mitrovic, S. Taylor, P. Chalker Study On The Interface Properties And Reliability Of The Electric-Double-Layer Gate Dielectric For Hf-In-Zn-O MIS Capacitors H. Wang, Y. Li, X. Zou Photo-Induced Instability And Temperature Dependence Of Amorphous In-Ga-Zn-O Thin Film Transistors J. Chen, J. Xu, M. Wang, L. Cai The Worst Stress Condition Of Hot Carrier Degradation On High Voltage LDMOSFET S. Huayang, Y. Song, Z. Song, L. Yanju, A. Yong, J. Wu, V. Chang, K. Chien Visualization Of Crystalline Defects In Silicon, A Cause Of Electrical Leakage In Semiconductor Devices S. Chow, S. Lee, K. Lim, B. Khoo, C. Fu, X. Li Voltage Dependence And AC Life Time Of PMOS HCI J. Jia, P. Liu, F. Xue, J. Tien, A. Cai, F. Dhaoui, P. Singaraju, F. Hawley, J. McCollum Analysis Of Solder Bump Electromigration Reliability H. Ceric, R. Orio, S. Selberherr Au Electromigration And Ti Segregation In TiPtAu Gate Of PHEMTs Y. Huang, X. Hong, S. Li Effect Of Via Geometry On Thermal Stress In Dual-Damascene Cu Interconnects L. Chen, C. Li A Study Of The Mechanical Reliability Of A MEMS Microphone W. Fang, Q. Huang Analysis Of Dummy-Gate Dual-Directional SCR (dscr) Device For ESD Protection Y. Wang, G. Lu, J. Cao, S. Jia, G. Zhang, X. Zhang Anomalous Degradation Behavior Of P-Type Polycrystalline Silicon Thin Film Transistors Under Negative Gate Bias Stress M. Zhang, W. Zhou, R. Chen, M. Wong, H. Kwok Bias Dependence Of Dose Rate Effects In The Irradiated Substrate PNP Transistors Y. Liu, Q. Shi, T. Zhang, Y. En, B. Li, Y. He Channel Thermal Noise Modeling And High Frequency Noise Parameters Of Tri-Gate FinFETs C. Mukherjee, C. Maiti Characteristic Analysis Of Total Dose Irradiation Annealing Effect In SOI NMOSFET Y. He, H. Luo, Y. En Deradation Characteristics And Analysis Of AlGaN/GaN High Electron Mobility Transistors Under Reverse Gate Bias Step Stress C. Zeng, Y. Wang, X. Hong, P. Lai, Y. Huang, Y. En Effect Of Gate Structures On ESD Characteristics In SOI MOS Device Y. He, H. Luo, Q. Xiao Failure Analysis Of TaN Thin Film Resistors For Microwave Circuits Q. Cao, Z. Song, F. Wang, B. Wang, Z. Song, Y. Hu Geometric Effect On InAs/GaAs Quantum Dot Lasers Analyzed With The Aid Of EDX Mapping R. Wang, K. Yee, R. Phua Reliability Of 10Gb/s 850nm Oxide Confined Vertical Caviry Surface Emitting Lasers H. Meng, Z. Zhang, S. Wang, G. Ding, Z. Zhou Using Strain To Increase The Reliability Of Scaled Spin MOSFETs D. Osintsev, V. Sverdlov, A. Makarov, S. Selberherr The Evaluation Of Quality And Reliability Management System In The Foundry Process X. Zhang, Y. En Failure Analysis For Via With Solder Bubble Y. Wang, D. Luo Author Index

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