DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING, THE UNIVERSITY OF NEW MEXICO ECE-238L: Computer Logic Design Fall Notes - Chapter 6.

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1 PARTMNT OF LCTRICAL AN COMPUTR NGINRING, TH UNIVRSITY OF NW MXICO C-238L: Computer Logic esig Fall 23 RGISTRS: Notes - Chapter 6 -bit Register: This is a collectio of '' -type flip flops, where each flip flop idepedetly stores oe bit. The flip flops are coected i parallel. They also share the same '' ad 'clock' sigals bit Shift register: This is a collectio of '' -type flip flops, coected serially. The flip flops share the same '' ad 'clock' sigals. The serial iput is called '', ad the serial output is called ''. The flip flop outputs (also called the parallel output) is called =. epeg o how we label the bits, we ca have: right shift register: The iput bit moves from the MSB to the LSB, ad left shift register: The iput bit moves from the LSB to the MSB. RIGHT SHIFT RGISTR: LFT SHIFT RGISTR: Istructor: aiel Llamocca

2 PARTMNT OF LCTRICAL AN COMPUTR NGINRING, TH UNIVRSITY OF NW MXICO C-238L: Computer Logic esig Fall 23 Parallel access shift register: This is a shift register i which we ca write data o the flip flops i parallel. The figure below shows a 4- bit parallel access shift register s_l 2 s_l Adg eable to flip flops: I may istaces, it is very useful to have a sigal that cotrols whether the value of the flip flop is kept. The followig circuit represet a flip flop with sychroous eable. Whe =, the flip flop keeps its value. Whe =, the flip flop grabs the value at the iput. We ca thus create -bit register ad -bit shift registers with eable. Here, all the flip flops share the same eable iput. RGISTR: RIGHT SHIFT RGISTR: LFT SHIFT RGISTR: Istructor: aiel Llamocca

3 PARTMNT OF LCTRICAL AN COMPUTR NGINRING, TH UNIVRSITY OF NW MXICO C-238L: Computer Logic esig Fall 23 SYNCHRONOUS COUNTRS Couters are useful for: coutig the umber of occurreces of a certai evet, geerate time itervals for task cotrol, track elapsed time betwee two evets, etc. Couters are made of flip flops ad combiatorial logic. They are usually desiged usig Fiite State Machies (FSM)s. Sychroous couters chage their output o the clock edge (risig or fallig). ach flip flop shares the same clock iput sigal. If the iitial cout is ero, each flip flop shares the iput sigal. COUNTR CLASSIFICATION: a) Biary couter: A couter couts from to 2. The figure depicts a 2-bit couter. b) Modulus couter: A couter couts from to N-. Special case: BC (or decade) couter: Couts from to 9. 4 BC couter c) Up/dow couter: Couts both up ad dow, uder commad of a cotrol iput. d) Parallel load couter: The cout ca be give a arbitrary value. e) Couter with eable: If eable =, the cout stops. If eable =, the couter couts. This is usually doe by coectig the eable iputs of the flip flops to a sigle eable. f) Rig couter: Also called oe-hot couter (oly oe bit is at a time). It ca be costructed usig a shift register. The output of the last stage is fed back to the iput to the first stage, which creates a rig-like structure. The asychroous sigal start sets the iitial cout to (first bit set to ). xample (4-bits):,,,,, The figure below depicts a rig couter. 2 - start pr g) Johso couter: Also called twisted rig couter. It ca be costructed usig a shift register, where the output of the last flip flop is fed back to the first stage. The result is a couter where oly a sigle bit has a differet value for two cosecutive couts. All the flip flops share the asychroous sigal, which sets the iitial cout to. xample (4 bits):,,,,,,,,, The figure below depicts a Johso couter. 2 - Istructor: aiel Llamocca

4 PARTMNT OF LCTRICAL AN COMPUTR NGINRING, TH UNIVRSITY OF NW MXICO C-238L: Computer Logic esig Fall 23 FINIT STAT MACHINS: Sequetial circuits are also called Fiite State Machies (FSMs), because the fuctioal behavior of these circuits ca be represeted usig a fiite umber of states (flip flop outputs). The sigal sets the flip flops to a iitial state. Classificatio: - Moore machie: Outputs deped solely o the curret state of the flip flops. - Mealy machie: Outputs deped o the curret state of the flip flops as well as o the iput to the circuit. Oly for Mealy Machie Iputs Combiatorial Circuit Flip Flops (states) Combiatorial Circuit Outputs clock Ay geeral sequetial circuit ca be represeted by the figure above (Fiite State Machie model). A sequetial circuit with certai behavior ad/or specificatio ca be formally desiged usig the Fiite State Machie method: drawig a State iagram ad comig up the xcitatio Table. esigig sequetial circuits usig the Fiite State Machie method is a powerful i igital Logic esig. xample: 2-bit gray-code couter with eable ad output:,,,,, The output is whe the preset cout is. First step: raw the State iagram ad State Table. If we were to implemet the state machie i VHL, this is the oly step we eed. = / / / S / S4 / / S2 / S3 / / PRSNT STAT S S2 S3 S4 S S2 S3 S4 NXT NXT STAT COUNT S S2 S3 S4 S2 S3 S4 S Secod step: State Assigmet. We assig uique flip flop states to the our state labels (S, S2, S3, S4). Notice that this is arbitrary. However, we ca save resources if we assig each state to the cout that we desire. The, the output cout is just the flip flops outputs. S: = S2: = S3: = S4: = Istructor: aiel Llamocca

5 PARTMNT OF LCTRICAL AN COMPUTR NGINRING, TH UNIVRSITY OF NW MXICO C-238L: Computer Logic esig Fall 23 Third step: xcitatio table. Here, we replace the state labels by the flip flop states: PRSNT STAT NXTSTAT (t) (t) (t+) (t+) Fourth step: xcitatio equatios ad miimiatio. (t+) ad (t+) are the ext state of the flip flops, i.e. these sigals are to be coected to the iputs of the flip flops. (t+) (t+) + = + + = + = Fifth step: Circuit implemetatio: clock state S S S2 S3 S3 S4 S4 S S2 S2 Istructor: aiel Llamocca

6 PARTMNT OF LCTRICAL AN COMPUTR NGINRING, TH UNIVRSITY OF NW MXICO C-238L: Computer Logic esig Fall 23 Modifyig the rate of chage of a Fiite State Machie: We usually would like to reduce the rate at which FSM trasitios occur. A straightforward optio is to reduce the frequecy of the clock iput. But this is a very complicated problem whe a high precisio clock is required. Alteratively, we ca reduce the rate at which FSM trasitios occur by iclug a eable sigal i our FSM. The we assert the eable sigal oly whe we eed it. The effect is the same as reducig the frequecy of the iput clock. The figure below depicts a couter modulo-n (from to N-) that geerates a pulse (output sigal ) of oe clock period every time we hit the cout N-. The umber of bits the couter is give by = log. The effect is the same as reducig the frequecy of the FSM to, where is the frequecy of the clock. A modulo-n couter is better desiged usig VHL behavioral descriptio, where the cout is icreased by every clock cycle ad is geerated by comparig the cout to N-. A modulo-n couter could be desiged by the State Machie method, but this ca be very cumbersome if N is a large umber. For example, if N =, we eed states. Iputs FSM Outputs clock couter to N- As a example, we provide the timig diagram of the couter from to N-, whe N=. otice that is oly activated whe the cout reaches. This sigal cotrols the eable of a state machie, so that the FSM trasitios oly occur every clock cycles, thereby havig the same effect as reducig the frequecy by. Istructor: aiel Llamocca