ITRS 2013 Silicon Platforms + Virtual Platforms = An explosion in SoC design by Gary Smith
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1 ITRS 2013 Slcon Platforms + Vrtual Platforms = An exploson n SoC desgn by Gary Smth Gary Gary Smth Smth EDA, EDA, Inc. Inc. All All Rghts Rghts Reserved. Reserved. 1
2 The Fve Desgn Constrants Frequency Power Gate Count Desgn tme Cost of desgn Cost of the packaged SoC
3 What Happened to Performance? The old vew Frequency = Performance. Frequency s stll a constrant but Today s vew Performance = Latency plus Power Customer vew of Performance = Avalable Applcatons Gate count 3
4 Improvng Power s Impact on Desgn Table DESN14 Low-Power Desgn Technology Improvements and Impact on Dynamc and Statc Power Software Vrtual Prototype % 120% Vrtualzaton tools to allow the programmer to develop software pror to slcon Frequency Islands % 100% Desgnng blocks that operate at dfferent frequences Extreme Power Gatng % 100% Shuttng down applcatons (Dark Slcon) Hardware/Software Co- Parttonng Heterogeneous Parallel Processng (AMP) % 100% Hardware/software parttonng at the behavoral level based on power % 100% Usng multple types of processors n a parallel computng archtecture Many Core Software Development Tools % 100% Usng multple types of processors n a parallel computng archtecture Power-Aware Software % 100% Developng software usng power consumpton as a parameter Near-Threshold Computng % 80% Lowerng Vdd to mv Asynchronous Desgn % 100% Total Non-clock drven desgn Source: ITRS
5 Gates & Frequency (5 watts max) 14,000 12,000 10,000 8,000 6,000 4,000 2, , , , , , ,884 2,201 1,680 1, , Source: ITRS/Gary Smth EDA 2012 Total Gates n Mllons Ave Frequency n GHz 5
6 Max Usable Gates do to Power Constrants In 2011 we could use 39% of the avalable gate count. By 2026 we are up to 93% of the avalable gates, as long as we can accomplsh the requred mprovements. But now we need to look at cost. 6
7 Improvements on Desgn Productvty DT Improvement Year Productvty Delta Productvty (Gates/Year/Desgner) Cost Component Affected Descrpton of Improvement Software Vrtual Prototype % SW 1200K HW, 2584K SW SW development Vrtualzaton tools used to allow development pror to completed slcon Intellgent Testbench % HW 1650K HW, 2584K SW System desgn and verfcaton Reusable Platform Blocks Lke RTL verfcaton tool sute, but also wth automaton of the verfcaton parttonng step % HW, 100% SW 4949K HW, 5168K SW Chp/crcut/PD verfcaton Fully functonal platforms used as a block n larger platform desgn (e.g., ARM n OMAP) Slcon Vrtual Prototype % HW 9897K HW, 5168K SW System desgn and verfcaton Heterogeneous (AMP) Parallel Processng A hardware vrtualzaton platform that enables an RTL handoff of a SOC % HW, 100% SW 19794K HW, 10336K SW SW development verfcaton Many specalzed cores provde processng around a man processor, whch allows for performance, power effcency, and hgh reuse Transactonal Memory % SW SW Development Automatcaly handles locks and unlocks. Many-Core SW Development Tools % SW 19794K HW, 16537K SW SW development Enables complaton and SW development n hghly parallel processng SOCs Parallel SW Language % SW SW development Laguages specfcally desgned for parallel programng. Suoer Computer Class Servers System-Level Desgn Automaton (SDA) Executable Specfcaton Source: ITRS % HW 75% SW HW & SW Desgn and Development % HW, 37.5% SW 31671K HW, 45476K SW System desgn and verfcaton % HW, 200% SW 95013K HW, K SW System desgn and verfcaton Parallel computng specalsed for the applcaton and computer language. Automates true system desgn on- and off-chp for the frst tme, ncludng electronc, mechancal and other heterogeneous technologes Descrbes the system specfcaton n a manner that allows automated desgn and valdaton 7
8 Max Usable Gates at 5 Watts - Cost SW Cost n Mllons HW Cost n Mllons Source: ITRS
9 Cost of a 5 watt Moble SoC Desgn Only four tmes n 17 years wll we be able to meet our $50,000,000 goal for a large semconductor company desgn. We aren t even close to meetng the $25,000,000 goal for a VC funded Start-Up desgn. So f we can t use the maxmum allowable gate count, for our Power Budget, what can we do? 9
10 6,000 5,000 4,000 3,000 2,000 1,000 - Gates & $50m (5 watts max) , , , ,750 2, ,600 1, ,287 1,300 1, Total Gates n Mllons Ave Frequency n GHz Source: ITRS/Gary Smth EDA
11 Max Usable Gates at 5 Watts $50m Cost SW Cost n Mllons HW Cost n Mllons Source: ITRS/Gary Smth EDA
12 Gate Count of a 5 watt Moble, $50m SoC Desgn Not bad, n 2013 t s about the same gate count and by 2027 we can do 5,000,000,000 gates, vs. almost 13,000,000,000 usable gates. Now let s look at what a Start-Up can do. 12
13 3,500 3,000 2,500 2,000 1,500 1, Gates & 25M (5 watts max) , ,000 2, ,400 1, Total Gates n Mllons Ave Frequency n GHz Source: ITRS/Gary Smth EDA
14 Max Usable Gates at 5 Watts $25m Cost SW Cost n Mllons HW Cost n Mllons Source: ITRS/Gary Smth EDA
15 Gate Count of a 5 watt Moble, $25m SoC Desgn Agan not bad. They can come wthn both ther Power Budget and ther Cost Budget and desgn up to 3,000,000,000 gates. Now what does that mean to the marketng team. 15
16 Mllons of gates Gate Count by Cost Source: ITRS/Gary Smth EDA
17 The Compettve Edge So the more Apps you have on your phone the better chance you ll have a compettve edge. Stll they have to be the rght Apps. And let s face t 3 bllon gates s a LOT of gates. And how you use those gates s often more mportant that how many you use. 17
18 Bottom Lne There are predctons beng passed around that desgns wll cost $150 m. That s just wrong. You don t know the cost untl you pck a gate count. Truth s that s that f a Start-Up pcks ther product carefully, and does a smart desgn, they can compete. 18
19 ESL The Three Vrtual Prototypes The Archtect s Workbench Behavoral Level HW/SW Parttonng Archtectural Level SVP - The Slcon Vrtual Prototype SWVP - The Software Vrtual Prototype 19
20 The Slcon Vrtual Prototypes SVP 1, the desgn starts, hardware accelerators added, Transactonal Modelng developed. In-House Platforms desgned. SVP 2, exstng RTL blocks nserted, System C blocks syntheszed, desgn completed, desgn verfed, Golden Netlst s the output. Could be the same team. 20
21 The ESL Flow 2011 D e s g n ESL Desgn & Entry Excel Spreadsheet Desgn V e r f c a t o n Archtect s Workbench (SWVP 1) Valdaton (no models) Desgn D e s g n Software Vrtual Prototype (SWVP 2) Software Vrtual Prototype (SWVP 3) V e r f c a t o n Software Vrtual Prototype (SWVP 4) RTL Sgn-Off Apps 21
22 The ESL Flow 2012 D e s g n SoC Integraton Platform ESL Desgn & Entry V e r f c a t o n Desgn SVP Archtect s Workbench (SWVP 1) Valdaton (no models) Desgn D e s g n Software Vrtual Prototype (SWVP 2) Software Vrtual Prototype (SWVP 3) V e r f c a t o n Software Vrtual Prototype (SWVP 4) 22
23 The Software Vrtual Prototypes SWVP 1, the Archtect s Workbench, used by the Archtectural Team for desgn formaton and exploraton, usually modeled n C/C++ or M (Mathwork s Language). Mcroprocessors selected, Foundaton Platform selected, some Applcatons Platforms selected. 23
24 The Software Vrtual Prototypes SWVP 2, Applcatons code wrtten. Applcatons code s run on the SVP checkng for latency and power. SWVP 3, Frmware & Mddleware wrtten. Applcatons code s run on the SVP checkng for fnal latency and power. SWVP 4, Used by product marketng and sales to check out the desgn wth prospectve customers for possble modfcatons. 24
25 The Software Vrtual Prototypes The four dfferent SWVPs serve four dfferent functons, therefore there are: four dfferent users, four dfferent specfcatons, and four dfferent prce ponts! 25
26 The ESL Flow 2013 Numbers 129,346 17,435 D e s g n Slcon Vrtual Prototype (SVP 1) Slcon Vrtual Prototype (SVP 2) Desgn V e r f c a t o n Could be same Engneers Archtect s Workbench (SWVP 1) Valdaton Emulaton & Acceleraton (hardware) Desgn Verfcaton Desgn Software Vrtual Prototype (SWVP 2) Mddleware 262,074 Software Vrtual Prototype (SWVP 3) D e s g n Frmware 64,673 V e r f c a t o n Total SWVP 3 = 326,747 Prototypng System (hardware) Apps Code 578,677 Demo (hardware)) Small number 26
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