Layout Design II. Lecture Fall 2003

Transcription

1 Layout Design II Lecture Fall 2003

2 Roadmap Today: Layout Verification & design in the large Next week: Transistor sizing Wires Homework 1: Due Today Homework 2: Out Today, Due Sept 18 Lab 2: This week Lab 3: Warning! Work hard, keep working 2003 Herman Schmit

3 Today s Overview Handout: Virtuoso Design Verification DRC: Design Rule Check LVS: Layout versus Schematic Design in the large How do designers design ICs NOW 2003 Herman Schmit

4 Outline Reasoning Design Rule Checker (DRC) Extractions Layout vs. Schematic (LVS) SPICE Simulations

5 Reasoning Manufacturing is expensive Mask Set Cost $$$ millions Fab turn-around time is couple of months Make sure the timing requirements are met Process requirements are satisfied in the layout The layout implements correct functionality

6 Design Rule Checker (DRC) Each process has a set of design constraints Space rules Width rules Overlap/Extension rules Area/Density rules Design must be free from these errors in order to successfully manufacture an IC DRC tool is used to identify process violations present in the layout

7 Layout

8 Layout

9 DRC Window

10 Layout After DRC Run

11 Layout After DRC Run

12 Error Messages Windows

13 Fix the Layout OLD NEW

14 Extractions Polygons Devices Step Find FETs Calculate capacitances for FETs/wires Calculate resistances for FETs/wires

15 Starting

16 Extract Options LVS Options SPICE Options

17 Layout vs. Schematic (LVS) Does your layout match the schematic Does not perform functional checking In order to ensure schematic functionality at layout level, the LVS cannot generate any errors

18 LVS Example

19 LVS Example

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22 The net-lists failed to match Like matching is enabled. Using terminal names as correspondence points. Net-list summary for extracted view count 6 nets 3 terminals 3 pmos 3 nmos Net-list summary for schematic count 7 nets 5 terminals 3 pmos 3 nmos

23 The net-lists failed to match. layout schematic instances un-matched 2 2 rewired 0 0 size errors 0 0 pruned 0 0 active 6 6 total 6 6 nets un-matched 2 3 merged 0 0 pruned 0 0 active 6 7 total 6 7 terminals

24 devbad.out: I /M1? Device does not cross-match. I /M2? Device does not cross-match. netbad.out: N /net20? Net does not cross-match. It has 4 connections. N /gnd!? Net does not cross-match. It has 4 connections. N /net24? Net does not cross-match. It has 2 connections.

25 LVS Example

26 LVS Example

27 That s how we verify in 322 Simulate (Spice/Verilog) Compare (LVS) Make sure it could be fabbed (DRC) Full-custom design Useful in 1980s Still used in some portions of highest performance chips Microprocessors 2003 Herman Schmit

28 Design Productivity Crisis Transistors/chip [k] 1,000,000 10,000, Staff Yrs. 100,000 1,000,000 10, ,000 1, Staff Yrs. 10, SEMATECH * 2003 Herman Schmit 1000 * * Transistors/Staff-No Year

29 ASIC Design Abstractions Designer Productivity is THE big problem In 1978, people could draw transistors, now there are 100s of millions per chip New abstractions necessary: Masks Design Rules Layout Design Cell Libraries Std Cell Design????/???? Herman Schmit Current ASICs

30 Standard Cell Design Process Design Entry and Simulation» Schematics» Verilog / VHDL Logic Synthesis» Input: Verilog/VHDL and Cell Library» Estimated Timing» Simulation Timing Analysis» Determine worst-case clock speed Formal Verification» Check equivalence of Gates and Specification Design Hand-off 2003 Herman Schmit

31 Standard Cell Design Process Floorplanning» Localize major functions of the chip» Consider global timing» Partition design Placement» Find locations for all circuits» Consider detail timing» Assure proximity of critical nets Global Routing» Resolve congestion» Localize nets» Give critical nets best paths Detail Routing» Locate shortest paths» Create net geometry» Route critical nets first Tape-out to manufacturing 2003 Herman Schmit

32 Anatomy of a Standard Cell nwell Contact VDD Rail Nwell Signal Pins (metal 2) Metal 2 Pitch GND Rail Cell Width 2003 Herman Schmit Substrate Contact

33 Standard Cell Rows Shared VDD Shared Well Shared GND 2003 Herman Schmit

34 Standard Cell Rules Rails and wells route by abutment: Same width, spacing, metal layer Go to cell boundary Substrate or well contacts underneath Any other cell could abut All design rules enforced 50% to Boundary 2003 Herman Schmit

35 Standard Cell Libraries > 100 cells of different types Logic DFFs: Set/Reset polarity, scan variations Filler w/ Capacitors Library variations Low power, low leakage High performance Robust Data path oriented 2003 Herman Schmit

36 D Flip Flop: Standard Cell 2003 Herman Schmit

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44 History of Design Automation Periodic Periodic increases in abstraction to increase productivity The The next quantum step in productivity???? Results (Design Productivity) 1999 What s next? Synthesis 1978 a 0 d b 1 s clk q Schematic Entry Transistor Entry Effort (EDA tools effort) 2003 Herman Schmit

45 Productivity Gap: Core-based Design DSP core (bought) Kbrd cntrl RF Dsply cntrl Internal IP Core-based Design IP-based Design System-on-a-Chip (SoC) 2003 Herman Schmit Soft cores Synthesizable HDL Test-vectors Redesign in new process Hard cores Complete Layout Scale to new process New Class of Companies: IP-providers

46 Core-based Design Challenges System-on-a-Chip (SoC) Interfacing: How to get these blocks talking? Standard Busses: But then why have it on-chip? Debug: How to see embedded signals Testing: How to test individual cores? Liability/Support: What if there s a bug in one of the cores? Who will PAY! 2003 Herman Schmit

47 Summary Basic Layout using Virtuoso Layout Verification for 322 DRC LVS Design in the large Building standard cells Using a library of standard cells and design automation to construct a BIG chip Design Productivity Problem 2003 Herman Schmit