EE241 - Spring 2013 Advanced Digital Integrated Circuits. Assigned reading. No new reading. Lecture 4: Transistor Models

Transcription

1 EE41 - Spring 013 Advanced Digital Integrated ircuits ecture 4: Transistor Models Assigned reading No new reading 1

2 Outline ast lecture Features of modern technologies This lecture Transistor modeling 3 Part : Models

3 Device Models Transistor models I- characteristics - characteristics Interconnect models R,, overed in EE141 5 Transistor Modeling Different levels: Hand analysis omputer-aided analysis (e.g. Matlab) Switch-level simulation (e.g. NanoSim) ircuit simulation (Hspice) These levels have different requirements in complexity, accuracy and speed of computation e are primarily interested in delay and energy modeling, rather than current modeling But we have to start from the currents 6 3

4 Transistor Modeling D Accurate I- equations ell behaved conductance for convergence (not necessarily accurate) Transient Accurate I- and Q- equations Accurate first derivatives for convergence onductance, as in D Physical vs. empirical from BSIM group 7 Transistor I- Modeling BSIM Superthreshold and subthreshold models Need smoothening between two regions EK/PSP One continuous model based on channel surface potential 8 4

5 A. MOS on-current and relationship to gate sizing MOS I- (BSIM) Start with the basics: I DS = ox ( Th - (x)) E I DS = ox ( Th - (x)) (d (x)/dx) hen integrated over the channel: I DS ox Th DS DS l Transistor saturates when GD = Th, - the channel pinches off at drain s side. I DS ox Th 10 5

6 MOS urrents (3nm MOS with >>1μm) 8.E-04 7.E-04 I DS [A] 6.E-04 5.E-04 4.E-04 3.E-04 Quadratic.E-04 1.E-04 0.E DS [] urrents according to the quadratic model orrect for long channel devices ( ~ m) 11 Simulated 3nm Transistor 6.0E E-04 I DS [A] 4.0E E-04 ~ inear.0e E E+00 = 3nm DS [] 1 6

7 Simulation vs. Model 8.00E E E E-04 Model Device 4.00E E-04.00E E E+00 Major discrepancies: shape saturation points output resistances 13 elocity Saturation v n (m/s) v sat = 10 5 onstant velocity E v sat eff onstant mobility (slope = µ) E c = 1.5 E(/µm) 14 7

8 Modeling elocity Saturation n (m/s) Fit the velocity-dependence curve E E 1 E eff v n 1/ n NMOS: n = PMOS: n = 1 E (/µm) 15 Modeling elocity Saturation A few approximations: (a) n, (b) n = 1, (c) piecewise n (m/s) n ` Piecewise n = 1 E c /= sat / E (/µm) 16 8

9 Approximation n 1) v = µ eff E, E < E I DS ox DS Th DS ) v = v sat, E > E c dsat =? I Dsat ox Dsat Th Dsat an be reduced to EE141 model by Dsat = const 17 MOS Models - body effect parameter From EES141 Rabaey, nd ed. 18 9

10 Unified MOS Model Model presented is compact and suitable for hand analysis. Still have to keep in mind the main approximation: that DSat is constant. hen is it going to cause largest errors? hen E scales transistor stacks. But the model still works fairly well. 19 Approximation n = 1, piecewise n = 1 is solvable, piecewise closely approximates v effe 1 E / E v sat, 0, v E E0 eff E E 0 sat Sodini, Ko, Moll, TED 84 Toh, Ko, Meyer, JSS 88 BSIM model 0 10

11 Drain urrent l e can find the drain current by integrating I DS = ox ( Th - (x)) v ox DS IDS Th DS 1 DS E In saturation: I DSat ox v sat Th Dsat I Dsat 1 Dsat ox E Dsat Th Dsat 1 Drain urrent in elocity Saturation Solving for Dsat l DSat Th E E Th And saturation current I DSat eff oxe Th E Th 11

12 elocity Saturation 6.0E E E-04 I DS [A] 3.0E-04.0E E E DS [] 3 elocity Saturation E is dependent an calculate DSat ( Th ~ 0.4) [] DSat [] For Th << E, DSat is close to - Th For large, DSat bends upwards toward E Therefore E can be sometimes approximated with a constant term 4 1

13 Drain urrent 6.0E-04 unified model 5.0E-04 simulation E I DS [A] 3.0E-04 linear vel. saturation 0.8.0E E-04 saturation E dsat DS [] 5 Application of Models: NAND Gate -input NAND gate DD B Out A Sizing for equal transistions: P/N ratio (-ratio) of 1.6 about Upsizing stacks by a factor proportional to the stack height 6 13

14 Transistor Stacks ith transistor stacks, DS, reduce. Unified model assumes DSat = const. For a stack of two, appears that both have exactly double R ekv of an inverter with the same width Therefore, doubling the size of each, should make the pull down R equivalent to an inverter out 7 elocity Saturation As ( - Th )/E changes, the depth of saturation changes I DSat eff oxe Th E Th For, DS = 1.0, E is ~0.75 ith double length, E is 1.5 (in this model) Stacked transistors are less saturated - Th = 0.6, I DSat ~ /3 of inverter I DSat (64%) Therefore NAND should have pull-down sized 1.5X heck any library NAND s 8 14

15 elocity Saturation How about NAND3? I DSat = 1/ of inverter I DSat (instead of 1/3) How about PMOS networks? NOR 1.8x, NOR3.4x hat is E for PMOS? 9 Next ecture ontinue transistor modeling, capacitance, leakage Delay modeling 30 15