Exercise 1: Control Functions

Transcription

1 Exercise 1: Control Functions EXERCISE OBJECTIVE When you have completed this exercise, you will be able to control the function of an asynchronous ripple counter. You will verify your results by operating a 4-bit ripple counter. DISCUSSION The 4 output bits of this ripple counter are labeled BIT1 through BIT4. CLOCK cycle (positive and negative transition, or edges). BIT1 divides the CLOCK input by 2. It takes 2 CLOCK cycles to generate 1 output cycle at BIT1. BIT2 does not change its state until clocked by BIT1. BIT1 must complete 1 cycle before BIT2 changes its state. BIT2 divides the CLOCK input by 4. It takes 4 CLOCK cycles to generate 1 output cycle at BIT2. FACET by Lab-Volt 31

2 Digital Circuit Fundamentals 1 Each counter section divides its respective input by 2. However, the relationship between weighted counter outputs and the CLOCK input is on a divide-by-2, -4, -8, or -16 basis. The four output bits of the ripple counter form a nibble, or half an 8-bit binary word. A nibble (4 bits) can be converted to a decimal (base 10) or hexadecimal ($) equivalent. A 4-bit ripple counter generates an output range equivalent to a. 0 through b. 0 through $F. c through d. All of the above. 32 FACET by Lab-Volt

3 PROCEDURE Locate the ASYNCHRONOUS RIPPLE COUNTER circuit block, and connect the circuit shown. Place the toggle switch on the PULSE GENERATOR in its UP position. NOTE: The UP LEDs (U) and the Down LEDs (D) represents a one (1) when on and a zero (0) when off. a. yes b. no How can you reset your ripple counter? a. Generate 15 or more clock pulses. b. Momentarily insert a two-post connector into the SET position. c. Momentarily insert a two-post connector into the CLEAR position. FACET by Lab-Volt 33

4 Digital Circuit Fundamentals 1 Reset your ripple counter. What values do the UP and DOWN LEDs indicate? NOTE: On your circuit block, the MSB stage is at the top, and the LSB stage is at the bottom. a. UP LEDs indicate $0; DOWN LEDs indicate $F. b. UP LEDs indicate $F; DOWN LEDs indicate $0. c. Both sets of LEDs indicate $0. d. Both sets of LEDs indicate $F. To clock, or increment, your counter, you must toggle the switch on the PULSE GENERATOR. The LS76 is a negative-triggered device. Therefore, the downward action of the switch does not clock the counter. The switch must be placed down then up to complete a count (one cycle). 34 FACET by Lab-Volt

5 Generate 5 CLOCK cycles with the PULSE GENERATOR toggle switch. NOTE: This requires 5 down-up switch movements. On your circuit block, the MSB stage is at the top, and the LSB stage is at the bottom. a (MSB to LSB) b (MSB to LSB) c (MSB to LSB) Based on the DOWN LED indication of 1010, the counter has a. complementary outputs. b. the ability to count up and down simultaneously. c. Both of the above. d. None of the above. FACET by Lab-Volt 35

6 Digital Circuit Fundamentals 1 Cycle the counter through its range. Based on your observations, do all the counter outputs change state on each clock cycle? a. yes b. no If your counter is preset, what UP LED binary pattern should you expect to see? pattern = (Recall Value 1) Preset your ripple counter. Then initiate one clock cycle. Based on your observation, the UP count a. increments by 1, while the DOWN count decrements by 1. b. decrements by 1, while the DOWN count increments by 1. c. Both of the above. Based on your observations, can you determine the maximum count indication of your ripple counter? a. Yes. The maximum count indication is ( ). b. No. Since each clock cycle alters the count value, a maximum count value cannot be determined. Place CM switch 10 in the ON position to pull PR low. Attempt to clear and cycle your counter. Based on your observations, the counter a. operates normally. b. does not respond to a CLEAR function. c. is momentarily reset but does not respond to CLOCK inputs. d. can indicate only 0 or FACET by Lab-Volt

7 CM 10 is still active. Use your multimeter to monitor the PR inputs. How does your measurement support the circuit operations? a. It doesn t. The circuit operation is inconsistent with the low meter indication (about 0 V). b. PR pulled low forces a constant SET operation. CLEAR active (pulled low) overrides SET (PR) operation. Place CM switch 10 in the OFF position. Place CM switch 12 in the ON position to disrupt the counting action of your circuit. Set and then clear your counter. The SET function appears to operate correctly, but the BIT2 DOWN LED does not respond to the CLEAR function. Monitor the CLOCK input to the BIT3 stage of your counter as you clock your counter. Based on your observations, the a. MSB and third stages of the counter are not clocked. b. LSB and second stages of the counter are not clocked. Place CM switch 12 in the OFF position. Based on your observations, can the operation of the ripple counter indicate circuit performance? a. yes b. no Make sure all CMs are cleared (turned off) before proceeding to the next section. FACET by Lab-Volt 37

8 Digital Circuit Fundamentals 1 CONCLUSION A ripple counter with complementary outputs can count up and down. CLEAR forces the UP outputs of a 4-bit ripple counter to SET forces the UP outputs of a 4-bit ripple counter to The outputs of a ripple counter need not change together. Each output section must be clocked by a preceding stage of the counter. REVIEW QUESTIONS 1. The counter you used in this exercise is a(n) a. binary counter. b. ripple counter. c. asynchronous counter. d. All of the above. 2. A ripple counter with complementary outputs can count a. up only. b. down only. c. up and down. d. None of the above. 3. A 5-stage ripple counter provides a frequency, or count, division of a. 32. b. 16. c. 8. d. None of the above. 38 FACET by Lab-Volt

9 4. a. 12. b. 9. c. 5. d. 3. NOTE: 5. With respect to the UP LEDs of your ripple counter, the CLEAR and SET functions a. generate 1111 and 0000, respectively. b. have no effect because one function cancels the other. c. generate 0000 and 1111, respectively. d. generate 0101 and 1010, respectively. FACET by Lab-Volt 39