VLSI Design I; A. Milenkovic 1

Transcription

1 State Registers Review: Sequential efinitis CPE/EE 427, CPE 527 VLSI esign I L2: ynamic Sequential Circuits epartment of Electrical and Computer Engineering University of labama in Huntsville leksandar Milenkovic ( www. ece.uah.edu/~milenka ) www. ece.uah.edu/~milenka/cpe527-3f Static versus dynamic storage static uses a bi element with feedback (regenerati) and thus preserves its state as lg as the power is static is preferred when updates are infrequent ( gating) dynamic stores state parasitic capacitors so ly holds the state for a period of (millisecds) and requires periodic refresh dynamic is usually simpler (fewer transistors), higher speed, lower power Latch versus flipflop latches arelevel sensitive with two modes: transparent - inputs are passed to and hold - output fliplflops are edge sensitive that ly sample the inputs a transiti [dapted from Rabaey s igital tegrated Circuits, 22, J. Rabaey et al. and Mary Jane Irwin ( www. cse. psu.edu/~mji ) ] /7/23 VLSI esign I;. Milenkovic 2 Review: Timing Metrics Review: System Timing Cstraints puts Combinatial Logic puts t su data t hold t c-q Current State Next State T ( period) output output t cdreg + t cdlogic t hold T t c-q + t plogic + t su /7/23 VLSI esign I;. Milenkovic 3 /7/23 VLSI esign I;. Milenkovic 4 ynamic ET Flipflop master slave! ynamic ET Flipflop master slave! T I M T 2 I 2 C! t su = t hold = t c-q = T I M T 2 I 2 C! t su = t pd_tx t hold = zero t c-q = 2 t pd_inv + t pd_tx!! /7/23 VLSI esign I;. Milenkovic 5 /7/23 VLSI esign I;. Milenkovic 6 VLSI esign I;. Milenkovic

2 ynamic ET FF Race Cditis ynamic Two-Phase ET FF! 2 T I M T 2 I 2 T I M T 2 I 2 C!! C!2! - overlap race cditi t overlap- < t T +t I + t T2 - overlap race cditi t overlap- < t hold 2 t n_overlap /7/23 VLSI esign I;. Milenkovic 7 /7/23 VLSI esign I;. Milenkovic Pseudostatic ynamic Latch Robustness csideratis limit the use of dynamic FF s coupling between signal nets and internal storage nodes can inject significant noise and destroy the FF state leakage currents cause state to leak away with internal dynamic nodes d t track fluctuatis in V that reduces noise margins simple fix is to make the circuit pseudostatic! MOS (Clocked CMOS) ET Flipflop -skew insensitive FF! M C M! M 7 dd above logic added to all dynamic latches /7/23 VLSI esign I;. Milenkovic 9! /7/23 VLSI esign I;. Milenkovic MOS (Clocked CMOS) ET Flipflop -skew insensitive FF MOS FF - Overlap Case Clock-skew insensitive as lg as the rise and fall s of the edges are sufficiently small! M C! M 7 M C M M!!! /7/23 VLSI esign I;. Milenkovic /7/23 VLSI esign I;. Milenkovic 2 VLSI esign I;. Milenkovic 2

3 Volts MOS FF - Overlap Case MOS Transient Respse! 3 For a 2.5 M M (3). ns C M 7 (3) 2.5 M (.) (.) For a.5 (3) 3 ns (race cditi! exists) overlap cstraint t overlap- < t hold Time (nsec) /7/23 VLSI esign I;. Milenkovic 4 /7/23 VLSI esign I;. Milenkovic 3 Pipelining using MOS Example V V V!! F G C M 7! C 3 M M NOR Logic What are the cstraints F and G? Number of a static inversis should be even /7/23 VLSI esign I;. Milenkovic 5 /7/23 VLSI esign I;. Milenkovic 6 NOR CMOS Modules True Single Phase Clocked (TSPC) Latches V V V Negative Latch Positive Latch 2 3 PUN PN Combinatial logic Latch (a) -module V V V V PN 4 (b) -module hold when = transparent when = transparent when = hold when = /7/23 VLSI esign I;. Milenkovic 7 /7/23 VLSI esign I;. Milenkovic VLSI esign I;. Milenkovic 3

4 Volts Embedding Logic in TSPC Latch TSPC ET FF PUN B M PN B /7/23 VLSI esign I;. Milenkovic 9 /7/23 VLSI esign I;. Milenkovic 2 TSPC ET FF Simplified TSPC ET FF M 6 M M X M M 7 /7/23 VLSI esign I;. Milenkovic 2 /7/23 VLSI esign I;. Milenkovic 22 Simplified TSPC ET FF Sizing Issues in Simplified TSPC ET FF M 6 M fi fi M 2 Xfi! M M M 7 fi 3 2! orig! mod Transistor sizing Original width, =.5µm M 7, = 2µm orig mod Time (nsec) Modified width, = µm M 7, = µm /7/23 VLSI esign I;. Milenkovic 23 /7/23 VLSI esign I;. Milenkovic 24 VLSI esign I;. Milenkovic 4

5 Split-put TSPC Latches Positive Latch Negative Latch Split-put TSPC ET FF M transparent when = hold when = hold when = transparent when = When =, = V - V Tn When =, = V Tp /7/23 VLSI esign I;. Milenkovic 25 /7/23 VLSI esign I;. Milenkovic 26 Pulsed FF (M-K6) Pulse registers - a short pulse (glitch ) is generated locally from the rising (or falling) edge of the system and is used as the input to the flipflop race cditis are avoided by keeping the transparent mode very short (during the pulse ly) advantage is reduced load; disadvantage is substantial increase in verificati complexity /Vdd / P / M / 2 P 2 M /7/23 VLSI esign I;. Milenkovic 27 X Vdd!d P 3 M 6 / Sense mp FF (Strgrm S) Sense amplifier (circuits that accept small swing input signals and amplify them to full rail-to-rail signals) flipflops advantages are reduced load and that it can be used as a receiver for reduced swing differential buses M M 6 /7/23 VLSI esign I;. Milenkovic 2 M 7 M! Flipflop Comparis Chart Choosing a Clocking Strategy Name Mux PowerPC 2-phase T-gate MOS TSPC S-O TSPC M K6 S Type Static Static Ps-Static ynamic ynamic ynamic ynamic ynamic Sensemp # ld (-!) (-!) (- 2) 4 (-!) 4 (-!) 4 () 2 () 5 () 3 () #tr t set -up 3t pinv +t ptx t ptx t pinv t hold t o- t pinv t pff t pinv +t ptx 2t pinv +t ptx 3t pinv Choosing the right ing scheme affects the functiality, speed, and power of a circuit Two-phase designs + robust and cceptually simple - need to generate and route two signals - have to design to accommodate possible skew between the two signals Single phase designs + ly need to generate and route e signal + supported by most automated design methodologies + d t have to worry about skew between the two s - have to have guaranteed slopes the edges /7/23 VLSI esign I;. Milenkovic 29 /7/23 VLSI esign I;. Milenkovic 3 VLSI esign I;. Milenkovic 5