VLSI Design I; A. Milenkovic 1

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1 Review: The Regenerative Property V i V o V i V o CPE/EE 47, CPE 57 VLSI esign I : Sequential Circuits epartment of Electrical and Computer Engineering University of labama in Huntsville leksandar Milenkovic ( ) V i = V o C cascaded inverters B If the gain in the transient region is larger than, only and B are stable operation points. C is a metastable operation point. V i = V o /7/5 VLSI esign I;. Milenkovic Bistable Circuits Review: SR The cross-coupling of two V i inverters results in a bistable circuit (a circuit with two stable states) V i Have to be able to change the stored value by making (or B) temporarily unstable by increasing the loop gain to a value larger than done by applying a trigger pulse at V i or V i the width of the trigger pulse need be only a little larger than the total propagation delay around the loop circuit (twice the delay of an inverter) Two approaches used cutting the feedback loop (mux based latch) overpowering the feedback loop (as used in SRMs) /7/5 VLSI esign I;. Milenkovic 3 S R! S!! memory set R disallowed /7/5 VLSI esign I;. Milenkovic 4 Review: Clocked! MU Based es Change the stored value by cutting the feedback loop feedback feedback transparent mode Negative Positive hold mode /7/5 VLSI esign I;. Milenkovic 5 = &! & transparent when the is low =! & & transparent when the is high /7/5 VLSI esign I;. Milenkovic 6 VLSI esign I;. Milenkovic

2 State Registers FF TG MU Based Implementation PT MU Based Implementation!! feedback (hold mode) /7/5 VLSI esign I;. Milenkovic 7! input sampled (transparent mode)! Reduced load, but threshold drop at output of pass transistors so reduced noise margins and performance feedback (hold mode) /7/5 VLSI esign I;. Milenkovic 8! input sampled (transparent mode) Race Problem Master Slave Based ET Flipflop B B B Which value of B is stored? M Slave Master Two-sided constraint = transparent hold M T t c-q t plogic t su T high < t c-q logic = hold transparent /7/5 VLSI esign I;. Milenkovic 9 /7/5 VLSI esign I;. Milenkovic Master MS ET Implementation Slave Master MS ET Implementation Slave I T I 3 M I 5 T 4 I 6 I T I 3 M I 5 T 4 I 6 I T T 3 I 4 I T T 3 I 4! master transparent slave hold! master hold slave transparent /7/5 VLSI esign I;. Milenkovic /7/5 VLSI esign I;. Milenkovic VLSI esign I;. Milenkovic

3 MS ET Timing Properties ssume propagation delays are t pd_inv and t pd_tx, that the contamination delay is, and that the inverter delay to derive! is Set-up time - time before rising edge of that must be valid Propagation delay -time for M to reach Hold time - time must be stable after rising edge of - MS ET Timing Properties ssume propagation delays are t pd_inv and t pd_tx, that the contamination delay is, and that the inverter delay to derive! is Set-up time - time before rising edge of that must be valid 3 * t pd_inv t pd_tx Propagation delay -time for M to reach t pd_inv t pd_tx Hold time - time must be stable after rising edge of zero /7/5 VLSI esign I;. Milenkovic 3 /7/5 VLSI esign I;. Milenkovic 4 Set-up Time Simulation Set-up Time Simulation Volts M I out t setup =. ns Volts M I out t setup =. ns Time (ns) works correctly Time (ns) fails /7/5 VLSI esign I;. Milenkovic 5 /7/5 VLSI esign I;. Milenkovic 6 Propagation elay Simulation Reduced Load MS ET FF Volts t c-q(lh) t c-q(hl) Time (ns) t c-q(lh) = 6 psec t c-q(hl) = 8 psec Clock load per register is important since it directly impacts the power dissipation of the network. Can reduce the load (at the cost of robustness) by making the circuit ratioed T! I M! T I I 4 reverse conduction to switch the state of the master, T must be sized to overpower I to avoid reverse conduction, I 4 must be weaker than I I 3 /7/5 VLSI esign I;. Milenkovic 7 /7/5 VLSI esign I;. Milenkovic 8 VLSI esign I;. Milenkovic 3

4 Non-Ideal Clocks Example of Clock Skew Problems!!! P P B P 3 I I I 3 I 4 P 4! Ideal s Non-ideal s skew - overlap - overlap /7/5 VLSI esign I;. Milenkovic 9! Race condition direct path from to during the short time when both and! are high (- overlap) Undefined state both B and are driving when and! are both high ynamic storage when and! are both low (- overlap) /7/5 VLSI esign I;. Milenkovic Pseudostatic Two-Phase ET FF Two Phase Clock Generator P B P 3 I I I 3 I 4! B P P 4 master transparent slave hold dynamic storage B t non_overlap master hold slave transparent /7/5 VLSI esign I;. Milenkovic /7/5 VLSI esign I;. Milenkovic Power PC Flipflop Power PC Flipflop!!!!! master transparent slave hold! master hold slave transparent /7/5 VLSI esign I;. Milenkovic 3 /7/5 VLSI esign I;. Milenkovic 4 VLSI esign I;. Milenkovic 4

5 Ratioed CMOS Clocked SR Ratioed CMOS Clocked SR! off M on M4! off on M on off M4 S M6 M5 off on M M3 off M8 M7 on R off->on M6 S M5 off M on off off->on M8 M3 off on M7 R on /7/5 VLSI esign I;. Milenkovic 5 /7/5 VLSI esign I;. Milenkovic 6 Sizing Issues Transient Response 3 SET! (Volts).5.5 so W/L 5and6 > 3 &! (Volts) t c-!! t c W/L 5and6 W/L and4 =.5µm/.5 µm W/L and3 =.5µm/.5 µm /7/5 VLSI esign I;. Milenkovic Time (ns) /7/5 VLSI esign I;. Milenkovic 8 6 Transistor CMOS SR Sequencing R S M M5! R M M4 M3 M6 S logic output depends on current inputs Sequential logic output depends on current and previous inputs Requires separating previous, current, future Called state or tokens Ex: FSM, pipeline in out Finite State Machine Pipeline /7/5 VLSI esign I;. Milenkovic 9 /7/5 VLSI esign I;. Milenkovic 3 VLSI esign I;. Milenkovic 5

6 State Registers State Registers Sequencing Cont. If tokens moved through pipeline at constant speed, no sequencing elements would be necessary Ex: fiber-optic cable Light pulses (tokens) are sent down cable Next pulse sent before first reaches end of cable No need for hardware to separate pulses But dispersion sets min time between pulses This is called wave pipelining in circuits In most circuits, dispersion is high elay fast tokens so they don t catch slow ones. /7/5 VLSI esign I;. Milenkovic 3 Sequencing Overhead Use flip-flops to delay fast tokens so they move through exactly one stage each cycle. Inevitably adds some delay to the slow tokens Makes circuit slower than just the logic delay Called Some people call this ing overhead But it applies to asynchronous circuits too Inevitable side effect of maintaining sequence /7/5 VLSI esign I;. Milenkovic 3 Sequential Timing Metrics In Out Inputs Outputs t su time Current State Next State In data stable t c-q time Out output stable output stable time /7/5 VLSI esign I;. Milenkovic 33 /7/5 VLSI esign I;. Milenkovic 34 System Timing Constraints Sequencing Elements Inputs Current State Outputs Next State T ( period) : Level sensitive a.k.a. transparent latch, latch Flip-flop: edge triggered.k.a. master-slave flip-flop, flip-flop, register Timing iagrams Transparent Opaque Edge-trigger reg logic T t c-q t plogic t su (latch) (flop) /7/5 VLSI esign I;. Milenkovic 35 /7/5 VLSI esign I;. Milenkovic 36 VLSI esign I;. Milenkovic 6

7 Sequencing Elements esign : Level sensitive a.k.a. transparent latch, latch Flip-flop: edge triggered.k.a. master-slave flip-flop, flip-flop, register Timing iagrams Transparent Opaque Edge-trigger (latch) (flop) Pass Transistor Pros Cons /7/5 VLSI esign I;. Milenkovic 37 /7/5 VLSI esign I;. Milenkovic 38 esign esign Pass Transistor Pros Tiny Low load Cons V t drop nonrestoring backdriving output noise sensitivity dynamic diffusion input Used in 97 s Transmission gate - /7/5 VLSI esign I;. Milenkovic 39 /7/5 VLSI esign I;. Milenkovic 4 esign esign Transmission gate No V t drop - Requires inverted Inverting buffer Fixes either /7/5 VLSI esign I;. Milenkovic 4 /7/5 VLSI esign I;. Milenkovic 4 VLSI esign I;. Milenkovic 7

8 esign esign Inverting buffer Restoring No backdriving Fixes either Output noise sensitivity Or diffusion input Inverted output Tristate feedback /7/5 VLSI esign I;. Milenkovic 43 /7/5 VLSI esign I;. Milenkovic 44 esign esign Tristate feedback Static Backdriving risk Static latches are now essential Buffered input /7/5 VLSI esign I;. Milenkovic 45 /7/5 VLSI esign I;. Milenkovic 46 esign esign Buffered input Fixes diffusion input Noninverting Buffered output /7/5 VLSI esign I;. Milenkovic 47 /7/5 VLSI esign I;. Milenkovic 48 VLSI esign I;. Milenkovic 8

9 esign esign Buffered output No backdriving Widely used in standard cells Very robust (most important) - Rather large - Rather slow (.5 FO4 delays) - High loading atapath latch - /7/5 VLSI esign I;. Milenkovic 49 /7/5 VLSI esign I;. Milenkovic 5 esign Flip- esign atapath latch Smaller, faster - unbuffered input Flip-flop is built as pair of back-to-back latches /7/5 VLSI esign I;. Milenkovic 5 /7/5 VLSI esign I;. Milenkovic 5 Enable Enable: ignore when en = Mux: increase latch - delay Clock Gating: increase en setup time, skew Reset Force output low when asserted Synchronous vs. asynchronous Symbol Symbol Multiplexer esign Clock Gating esign en en en en en en Synchronous Reset synchronous Reset /7/5 VLSI esign I;. Milenkovic 53 /7/5 VLSI esign I;. Milenkovic 54 VLSI esign I;. Milenkovic 9

10 Set / Reset Sequencing Methods Set forces output high when enabled Flip-flop with asynchronous set and Flip-flops -Phase es Pulsed es Flip-s set set -Phase Transparent es Pulsed es p t pw p / t nonoverlap Half-Cycle Half-Cycle t nonoverlap p /7/5 VLSI esign I;. Milenkovic 55 /7/5 VLSI esign I;. Milenkovic 56 Timing iagrams Max-elay: Flip-s Contamination and Propagation elays Y Y t pd tpd Tc ( 4443 ) F F t pd Prop. elay Cont. elay / Clk- Prop elay t setup thold t setup t pdq t setup / Clk- Cont. elay - Prop elay - Cont. elay / Setup Time / Hold Time t setup q t pdq t pd /7/5 VLSI esign I;. Milenkovic 57 /7/5 VLSI esign I;. Milenkovic 58 Max-elay: Flip-s Max elay: -Phase es ( setup ) tpd Tc t tpcq 443 F F t = t t Tc ( 4443 ) pd pd pd 3 L L3 3 t setup t pd t pdq t pd t pdq t pd 3 /7/5 VLSI esign I;. Milenkovic 59 /7/5 VLSI esign I;. Milenkovic 6 VLSI esign I;. Milenkovic

11 Max elay: -Phase es Max elay: Pulsed es ( ) t = t t Tc tpdq 3 pd pd pd 3 L L3 3 tpd Tc max 44 ( ) p L p t pdq (a) t pw > t setup t pd t pdq p t pd t pw tpd tsetup t pdq (b) t pw < t setup t pd 3 /7/5 VLSI esign I;. Milenkovic 6 /7/5 VLSI esign I;. Milenkovic 6 Max elay: Pulsed es Min-elay: Flip-s ( setup ) tpd Tc max tpdq, tpcq t tpw p L p t cd F t pdq (a) t pw > t setup t pd F p t pw tpd tsetup (b) t pw < t setup /7/5 VLSI esign I;. Milenkovic 63 /7/5 VLSI esign I;. Milenkovic 64 Min-elay: Flip-s Min-elay: -Phase es t t t cd hold ccq F t t cd, cd L F Hold time reduced by nonoverlap Paradox: hold applies twice each cycle, vs. only once for flops. But a flop is made of two latches! t nonoverlap /7/5 VLSI esign I;. Milenkovic 65 /7/5 VLSI esign I;. Milenkovic 66 VLSI esign I;. Milenkovic

12 Min-elay: -Phase es Min-elay: Pulsed es t t t t t cd cd ccq, hold nonoverlap L p tcd L Hold time reduced by nonoverlap Hold time increased by pulse width p Paradox: hold applies twice each cycle, vs. only once for flops. But a flop is made of two latches! t nonoverlap p tpw /7/5 VLSI esign I;. Milenkovic 67 /7/5 VLSI esign I;. Milenkovic 68 Min-elay: Pulsed es Time Borrowing t t t t cd hold ccq pw Hold time increased by pulse width p p L p tpw In a flop-based system: ata launches on one rising edge Must setup before next rising edge If it arrives late, system fails If it arrives early, time is wasted s have hard edges In a latch-based system ata can pass through latch while transparent Long cycle of logic can borrow time into next s long as each loop completes in one cycle /7/5 VLSI esign I;. Milenkovic 69 /7/5 VLSI esign I;. Milenkovic 7 Time Borrowing Example How Much Borrowing? -Phase es t T c ( tsetup t ) borrow nonoverlap L (a) Pulsed es t nonoverlap Borrowing time across half-cycle boundary Borrowing time across pipeline stage boundary t t t borrow pw setup / Nominal Half-Cycle elay t borrow t setup (b) Loops may borrow time internally but must complete within the cycle /7/5 VLSI esign I;. Milenkovic 7 /7/5 VLSI esign I;. Milenkovic 7 VLSI esign I;. Milenkovic

13 t skew Clock Skew Skew: Flip-s We have assumed zero skew Clocks really have uncertainty in arrival time ecreases maximum propagation delay Increases minimum contamination delay ecreases time borrowing cd hold ( setup skew ) tpd Tc tpcq t t t t t t ccq skew F t pdq t setup F t skew F F /7/5 VLSI esign I;. Milenkovic 73 /7/5 VLSI esign I;. Milenkovic 74 Skew: es Two-Phase Clocking -Phase es t Tc ( t ) pd pdq 3 t, t t t t t cd cd ccq hold nonoverlap skew t Tc ( tsetup t tskew ) borrow nonoverlap Pulsed es t Tc max ( tpdq, tpcq tsetup tpw tskew ) pd t t t t t cd hold pw ccq ( ) t t t t skew borrow pw setup skew 3 L L3 3 If setup times are violated, reduce speed If hold times are violated, chip fails at any speed In this class, working chips are most important No tools to analyze skew n easy way to guarantee hold times is to use - phase latches with big nonoverlap times Call these s, (ph, ph) /7/5 VLSI esign I;. Milenkovic 75 /7/5 VLSI esign I;. Milenkovic 76 Safe Flip- In class, use flip-flop with nonoverlapping s Very slow nonoverlap adds to setup time But no hold times In industry, use a better timing analyzer dd buffers to slow signals if hold time is at risk Summary Flip-s: Very easy to use, supported by all tools -Phase Transparent es: Lots of skew tolerance and time borrowing Pulsed es: Fast, some skew tol & borrow, hold time risk /7/5 VLSI esign I;. Milenkovic 77 /7/5 VLSI esign I;. Milenkovic 78 VLSI esign I;. Milenkovic 3