Impact of Reprocessing Technique on First Level Interconnects of Pb- Free to SnPb Reballed Area Array Flip Chip Devices

Transcription

1 Impact of Reprocessing Technique on First Level Interconnects of Pb- Free to SnPb Reballed Area Array Flip Chip Devices Joelle Arnold, Steph Gulbrandsen, Dr. Nathan Blattau IMAPS

2 Wait, what? o There s no prize for longest title? o Damn. 2

3 A Little Background o Impact of Reprocessing Technique on First Level Interconnects of Pb- Free to SnPb Reballed Area Array Flip Chip Devices o Reballing: replacement of existing solder spheres with new solder spheres, with the purpose of changing the solder alloy o Pb-Free to SnPb: Alloy change from a Pb-free alloy (such as SAC305) to eutectic SnPb o Adoption of RoHS and other legislation to restrict use of lead has made it increasingly difficult to procure BGAs with SnPb solder balls o High reliability applications that have not transitioned to a Pb-free assembly process are faced with a choice: custom order, reprocess, or adapt o First Level Interconnects: Wire bonds or C4 bumps between the die and the interposer; should not be affected by reballing 3

4 Abstract o The risk of damage caused by reballing a commercial off-the-shelf (COTS) active flip chip with a SAC305 ball grid array (BGA) to SnPb eutectic solder balls was studied o Five (5) different reballers were compared o Test vehicle was an active flip chip device o Eight (8) differential port pairs with pull-up resistors o Reballed components compared to one another and unreballed devices o Path resistance across differential port pairs o 2-dimensional x-ray microscopy o Acoustic microscopy o X-ray computer tomography (3-D x-ray) o These studies indicated that no measureable damage was incurred by the reballing process, implying that reballed devices should function as well as non-reballed devices o Caveat: this statement does not include the impact to the solder joints themselves 4

5 Introduction: Reballing Techniques o Reballing is both ball removal and ball attach o Ball removal melts off the pre-existing solder balls and prepares the solder pads for new solder balls o Two types of techniques o Ball attachment is the placement of new solder spheres on the pads and reflowing them to form an intermetallic bond o All reballers studied use comparable methods for ball attach 5

6 Introduction: Ball Removal Techniques o Two types of procedures for removal of solder spheres: 1. Melt the lead-free spheres with a hot implement (soldering iron) to remove the liquid solder by wick absorption 2. Dissolution of the lead-free spheres by touching them to a tin-lead molten solution (wave or fountain) 6

7 Dressed Pads Comparison A B C D E Direct light source, potential differences between approaches noted in strength of pink reflectance (B) and size of reflected ring light (E) 7

8 X-Ray Images After Ball Removal VSC3312 flip-chip x-ray image with examples of key features indicated. Solder bumps (first level interconnects) - yellow circles. Plated through holes in component substrate - red arrows. Solder pads from which balls have been removed - blue dotted circles. Dressed pads on VSC3312 flip chip; solder visible as radiopacity. Dark pads on left image indicate thicker coverage than faintly visible pads on right image. 8

9 Introduction: Ball Placement o Ball placement techniques and tooling are widely considered trade secrets o All reballers surveyed employ stencils to align new solder spheres with dressed pads 9

10 Focus o Does reballing the second level interconnects (B) damage first level interconnects (A)? 10

11 Test Vehicle: Active Flip Chip o Vitesse VSC3312 crosspoint switch o o I/O, 1.0mm pitch 15mm square package, 3mm die

12 Test Vehicle: Active Flip Chip o Eight (8) input pair circuits o Two 50Ω pull-up resistors between true and complement o Manufacturer specifies 85Ω to 125Ω as acceptable range 12

13 Sample Preparation o Ten (10) flip chips sent to each reballer o Instructed to perform ball removal as they normally would o Removal of SAC305 spheres o Cleaning and dressing solder pads o Instructed to simulate ball attach without applying spheres or paste o Reflow o Cleaning o Bakeout o Packages returned with no solder balls o Facilitate resistance probing 13

14 Sample Preparation, cont. o Upon receipt, components reflowed to simulate assembly Simulated Reflow of Active Flip Chip Components 225 SAC305 Liquidus 200 Temperature ( C) SnPb Liquidus Reballer A Reballer B Reballer C Reballer D Reballer E Time (s) 14

15 Reballing Techniques o Five reballers employing distinct techniques were audited during reballing of ball grid arrays o Reballers identified as A, B, C, D, & E o Reballers B and D remove solder balls with Technique 1 (soldering iron) o Reballers A, C, and E remove solder balls with Technique 2 (solder fountain) o Control o SAC305 components from same population as those sent for reballing o Solder balls removed mechanically o No thermal exposure o Low speed shear with XYZTEC Condor Classic Bond Tester 15

16 Results: Electrical Characterization o All measurements for all components within 85Ω and 125Ω range in specification o Five (5) components probed per population o Eight (8) probe pairs per component 16

17 What are Contour Plots o A contour plot is a graphic representation of the relationships among three numeric variables in two dimensions. Two variables are for X and Y axes, and a third variable Z is for contour levels. The contour levels are plotted as curves; the area between curves can be color coded to indicate interpolated values. (1) o You can interactively identify, label, color, and move contour levels, and change the resolutions of rectangular grids to get better contouring quality and performance o The plots on the next slide demonstrate that 95% of the time a resistance reading from the reballed population will overlap with that of the non-reballed population. Each plot indicates reballed and control populations of an I/O pair, and all the plots maintain the same behavior with 95% confidence. 1) SAS Institute Inc.,SAS/INSIGHT User s Guide, Version 8, Cary, NC: SAS Institute Inc., pp 17

18 Results: Electrical Characterization, cont. Independence of A1-AN1 Resistance for Reballed Flip Chip Populations Independence of A3-AN3 Resistance for Reballed Flip Chip Populations Independence of A4-AN4 Resistance for Reballed Flip Chip Populations Independence of A7-AN7 Resistance for Reballed Flip Chip Populations Independence of A8-AN8 Resistance for Reballed Flip Chip Populations Std Std Std Std Std Mean Mean Mean Mean Mean Independence of A0-AN0 Resistance for Reballed Flip Chip Populations Independence of A10-AN10 Resistance for Reballed Flip Chip Populations Independence of A11-AN11 Resistance for Reballed Flip Chip Populations 2.50 Std Std 2.00 Std Mean Mean o Contour plots demonstrate overlap between most populations o 95% confidence limit o Reballer D may be distinguishable from Reballers A and B o Not distinguishable from Reballers C, E, or control Mean 18

19 Results: Scanning Acoustic Microscopy (SAM) o Tomographic acoustic micro-imaging (TAMI) performed o One flip chip per population o Focused on two interfaces o Where C4 bumps adhere to pads on the die o Where C4 bumps adhere to substrate o No observed gaps, voids, or delamination on reballed or control components 19

20 Results: TAMI-SAM, Die to Bump Interface A B C D E Control 20

21 Results: TAMI-SAM, Bump to Substrate Interface A B C D E Control 21

22 Results: X-ray Computed Tomography (CT) o Computed tomography generates a 3-D model from a series of x-ray slices o One flip chip per population o No cracks or defects observed on reballed or control components o Some voiding observed at bump to substrate interface 22

23 Results: CT, Bump Near Substrate Interface Slices A B C D E Control 23

24 Results: CT, Void Measurement o Slices through C4 bumps near substrate provide a snapshot of voiding in the first level interconnects o Images were threshold corrected in ImageJ o Enables estimation of percent voiding 24

25 Results: CT, Bump Near Substrate Interface Slices, Void Measurement A B C D E Control 25

26 Results: CT, Measured Voiding in C4 Bumps o No industry standard for voiding in C4 bumps o IPC-A-610E allows for 25% voiding in solder balls o Voiding was well below 25% for all reballers and control 26

27 Conclusions o Damage was not observed to the first level interconnects as the result of reballing: o No changes in the resistance across solder bump connected input differential ports o These measurements would be expected to change dramatically if cracking occurred in the C4 bumps o Acoustic microscopy indicated that no delamination occurred within the packages during the reballing process o No evidence of gross void formation or coalescence within the C4 bumps was detected by CT o Voiding in control unit was about the same as the average voiding for all samples scanned o Changes to the appearance of the C4 bumps that would indicate cracking or damage accumulation was not observed 27

28 Acknowledgment This work was supported by a Small Business Innovation Research Grant from the Office of the Secretary of Defense. The authors also wish to thank the participating reballers for their warm welcome and insight into reballing processes. Thanks Greg, for giving the talk. 28

29 Author Biography o o o 29 Joelle Arnold spent 8 years at DfR Solutions, focusing on root cause analysis of electronics, with specialization in solder joint reliability, fracture, fatigue mechanics of materials, and electrolytic capacitors Her B.S. is in Engineering: Materials Science from Franklin W. Olin College of Engineering and is nearing completion of her M.S. at University of Maryland, College Park She is now a Senior Reliability Engineer at MKS Instruments of Andover, MA