Dual Boost High Performances Power Factor Correction (PFC)

Transcription

1 Dual Boos High Performances Power Facor Correcion (PFC) C. Aaianese, Senior Member, IEEE - V. Nardi, Member, IEEE - F. Parillo - G. Tomasso, Member, IEEE Deparmen of Auomaion, Elecromagneism, Compuer Science and Indusrial Mahemaics Universiy of Cassino, via G. Di Biasio 4, I-4 Cassino (FR) - ITALY {aaianese, nardi, omasso}@unicas.i Absrac - In his paper a novel Power Facor Correcion (PFC) dual boos scheme is proposed. I is based on an opimized power sharing where he acive filering approach is used o increase he curren qualiy and a he same ime o reduce he swiching losses. A prooype of Dual Boos PFC conrolled by a FPGA evaluaion board was se up o implemen he proposed conrol sraegy. Boh he simulaion and experimenal resuls show ha he proposed sraegy for PFC achieves near uniy power facor and a no negligible swiching losses reducion. I. INTRODUCTION The use of Power Facor Correcion (PFC) is necessary in order o comply he recen inernaional sandards, such as IEC--- and IEEE-9. The PFC can reduce he line curren harmonics and a he same ime increase he energy efficiency allowing a reducion of he uiliy bills. In lieraure wo differen soluions are described in order o conrol boh line curren disorion and he power facor: he Power Facor Correcion (PFC) circui and he Fron End Inverer (FEI) []-[]. The former is generally used in low power applicaions, such as single phase residenial applicaions, where a bidirecional power flow is no required. The second, insead, is used in a wide power range and in paricular when four quadran operaions are required. In his paper, saring from he basic circui of fig., a novel dual boos soluion is presened. The proposed PFC is shown in fig. and i is based on a dual boos circui where he firs one (swich T p and choke L p ) is used as main PFC circui and where he second one (swich T p and choke L p ) is used o perform an acive filering. The purpose of he acive filering performed by he second boos circui is o increase he qualiy of he line curren and a he same ime o reduce he PFC oal swiching losses. The swiching losses reducion effec come from he differen values of boh he swiching frequency and curren ampliude of each swich. In paricular for he firs swich (in he following called main swich) high currens and low swiching frequency are used, while for he second swich (in he following called filering swich) he conrol algorihm imposes high swiching frequency and low curren. Because he speed of a classical DSP is no suiable o implemen he proposed quasianalog curren conrol a low cos FPGA has been used o conrol a kw prooype converer. II. PROPOSED PFC MODELLING AND CONTROLLING Wih reference o fig., by considering he PFC working in coninuous conducion mode, he following volage equaions are worked ou: where: d vg() = Lp ip() + fp() vd() d d vg() = Lp ip() + fp() vd() d vg Vg () = sin ( ω ) if Tp = ( swichon) f p = if Tp = ( swichoff ) if Tp = ( swichon) f p = if Tp = ( swichoff ) () () () i g V g D D i v g L T C + v d i g V g D ipfc i p D i p v g L p L p D D 6 C + v d ac main D D 4 ac main D D 4 T p T p - - Fig.. Classical PCF circui. Fig.. Proposed dual boos PCF circui /8/$. 8 IEEE 7

2 he source main volage and PFC commuaion funcions respecively represen. In paricular, he () can be wrien as follows: where: d vg() fp = ip() = d Lp d vg() vd() fp = ip() = d Lp d vg() fp = ip() = d Lp d vg() vd() fp = ip() = d Lp (4) () ip ip (6) because of he unidirecional ac/dc diode recifier of figures. Therefore, he conrol of he PFC currens i p and i p can be achieved only if he following condiion occurs: vd() > vg() (7) In paricular if he (7) is saisfied i is possible o conrol he derivaive of he oal PFC curren i PFC d d d ipfc = ip+ ip (8) d d d As described above, by using (4) and () he conrol of he PFC currens i p and i p can be achieved and, in paricular, i is possible o rack he desired value of boh he PFC reference currens evaluaed by using he conrol scheme of fig.. In his conrol scheme he magniude of he desired PFC curren i * PFC is deermined by using a PI regulaor which inpu is he difference beween he reference and acual oupu volage. In order o obain an uniy power facor, he argumen of he oal PFC curren is deermined by using he argumen of he line * v dc PI + - v dc i PFC φ v * i PFC + i p - i p -+ e ip b m Fig.. Conrol scheme of he proposed dual boos converer. b f T T volage. Once he desired oal PFC curren is achieved, wo curren conrols has o be performed for boh he PFC circuis. The main PFC is modulaed wih an hyseresis conrol by imposing he oal PFC curren i * PFC. A large hyseresis band b m allows o achieve low swiching frequency. The filering PFC reference curren is, insead, he difference beween i * PFC and he acual value of i p. An hyseresis conrol is also performed, bu using a small hyseresis band b f. By using his approach he main PFC is used o ransfer he desired power o he load while he filering PFC is conrolled in order o increase he oal PFC curren qualiy. III. DUAL BOOST PFC EFFICIENCY The main goal of he proposed dual boos PFC and of he above described conrol algorihm is o inroduce improvemens in erms of power losses reducion hanks o an Acive Filering (AF) approach. The use of acive filering for his purpose is no new. In []-[6] his approach, called Moor Side Acive Filering (MSAF), is used in order o reduce he swiching losses of a Volage Source Inverer (VSI) parallel connecion for moor drive applicaions. The use of he acive filering for he swiching losses reducion is based on simple analysis of he linearized swiching characerisic of a power device. The oal swiching losses can be expressed by [7]: P = fvdciloadd (9) where f he swiching frequency, I load he device collecor curren, V dc he dc bus volage and d he urn-on and urn-off ime coefficien respecively represen. By using he (9) i is easy o show ha if he required load power is splied on wo differen swiches, operaing wih differen swiching frequency and wih differen currens, he oal efficiency is grealy improved wih respec o he case in which a single device is used. In paricular in he proposed approach he main PFC (swich T p ) works wih high curren and low swiching frequency while he filering PFC (swich T p ) works wih low curren and high swiching frequency. IV. DUAL BOOST PFC SIMULATION In order o perform a digial implemenaion of he conrol scheme shown in fig., an FPGA based archiecure has been chosen. This soluion, in fac, allows o obain boh he sabiliy of digial implemenaion and he performances of an analog circui. The proposed conrol scheme has been deeply esed in simulaion for a preliminary validaion. In paricular, a complee simulaion of boh he power elecronics sysem and of he conrol code has been performed by using he Malab Simulink and he Alera DSP Builder. I has o underline ha he use of he Alera DSP Builder allows o preliminary simulae he algorihm and hen o program direcly he FPGA saring from he Simulink code. Obviously his approach is 8

3 effecive only if all he conrol componens, included he digial and analogue I/O, are properly simulaed. Therefore he firs simulaion sep is he reproducion of all he analogue signal and heir quanizaion process as described in [6]. In fig. 4 he Simulink signals condiioning and A/D conversion code are shown. In fig. he hyseresis curren conrol performed by using he Alera DSP Builder is repored. In fig. 6 he main PFC curren obained wih an hyseresis band of A is shown. I can be seen ha an asymmerical hyseresis band has been used. By means of equaions (4)-(6), in fac, is possible o conrol he derivaive of boh he main and filering PFC currens bu i is no possible o compensae negaive errors of he main PFC curren. Thus, o avoid ha he quaniy e ip becomes negaive he lower value of he main PFC hyseresis band has been se o zero. Fig. 7 shows a deail of he main PFC curren, while in fig. 8 he filering PFC curren obained wih an hyseresis band of A is repored. As i is possible o see he ampliude of his curren is A which is he ampliude of he main PFC curren hyseresis band. The effec of he filering curren come clear in fig. 9 where a deail of main and filering curren is ploed. In fig he oal PFC curren is shown. In his las graph a no negligible reducion of he curren ripple is achieved. The ripple ampliude of he oal PFC curren is equal o A (fig.); which is he ampliude of he filering curren hyseresis band. V. EXPERIMENTAL RESULTS The performance of he proposed dual boos PFC has been experimenally invesigaed by using he kw prooype shown in fig., where he conrol uni is he Alera Ciclone FPGA while he power elecronic circui has been based on he Power Transisor SPPN6S and on he IR diode EPH6. The main PFC choke and he filering PFC choke are equal o.6 mh and.6 mh respecively. The FPGA used in he experimenal seup implemens he following funcions: o execue he conrol algorihm shown in fig. and in paricular perform a quasi-analog signal condiioning A/D conversion Fig.4. Simulink signal condiioning and A/D conversion. Fig.. Alera DSP Builder hyseresis curren conrol. Main PFC curren [A] Main PFC curren [A] Filering PFC curren [A] Main and Filering PFC currens [A] Fig.6. Simulaion resuls: main PFC curren Fig.7. Simulaion resuls:main PFC curren deail Fig.8. Simulaion resuls:filering PFC curren deail. reference curren reference curren main PFC curren main PFC curren main PFC curren filering PFC curren Fig.9. Simulaion resuls:deail of main and filering PFC currens. curren conrol by using he code of fig.; service of he A/D converer; shudown he PFC in he case of overcurren or overvolage. The resuls obained are repored in figs. -6. In fig. he ac main curren, he main PFC curren (i p ) and he filering PFC curren (i p ) respecively are shown. In his es he main PFC hyseresis band (b m ) is.a while he filering 9

4 Toal PFC curren [A] Toal PFC curren [A] Fig.. Simulaion resuls: oal PFC curren Fig.. Simulaion resuls: deail of oal PFC curren. PFC hyseresis band (b f ) is se o.a. This es validaes he he proposed acive filering approach; in paricular i shows ha he filering PFC curren (fig. c) allows o compensae he no negligible ripple of he main PFC curren (fig. b). In figure 4, a deail of he converer currens highligh he difference, in erms of swiching frequency, beween he main and filering PFC. In paricular he average value of boh he main and filering PFC swiching frequency is 4 khz and khz respecively. In fig. he same es is performed by using a main PFC hyseresis band of. A. Also in his case i is possible o obain a high qualiy line curren bu obviously an increase of he main PFC swiching losses has been paid. Fig. 6 shows he oscilloscope screensho of he es repored in figure. Several ess has been performed wih differen values of boh he hyseresis bands b f and b m in order o evaluae heir effec on he sysem efficiency. In paricular he swiching losses vs. he curren ripple of he proposed dual boos PFC is compared wih he one of a classical single boos PFC. To perform he above es he following curren ripple definiion has been used: T irip = ipfc () ipfc () d T irip irip % = * imax In fig. 7 a hermal image of he esed circui working in single boos mode (he filering PFC is disabled) is shown. As i is possible o see he swich emperaure reach 8. o C while he emperaure of he same swich, working in dual boos mode and a he same operaing condiion (curren ripple, curren ampliude and dc bus volage) is 7.4 o C (see fig. 8). The emperaure difference is deermined by he swiching losses reducion achieved by using he proposed dual boos circui. In paricular a oal losses reducion of 7% (main and filering swiching and conducion losses) has been evaluaed by using a calibraed hea sink mehod. This mehod consiss in he experimenal deerminaion of a hermal calibraion curve ha allows evaluaing he oal device/converer losses (swiching and conducion losses) simply by reading he componen emperaure. To deermine his hermal calibraion curve, by using a low power source, several DC curren have been injeced in he power device and, for each es curren, afer he sysem reached he hermal equilibrium, he device emperaure, he volage across he device V c and he injeced curren I c have been measured. A he seady sae he dissipaed power: P d = V c I c is sored and ploed as funcion of he device emperaure in order o deermine he hermal calibraion curve. In fig. 9 he above described hermal calibraion curve is shown. Moreover, by using his mehod i is also possible o deermine he device conducion losses as funcion of he device collecor curren, which is repored in fig.. I is possible o see ha, by means of he proposed approach, a 4% reducion of he swiching losses is achieved. CONCLUSION Fig.. Experimenal kw prooype board. In his paper a novel dual boos PFC circui is proposed and esed. By using he proposed power sharing conrol algorihm, based on acive filering approach, boh a reducion of swiching losses ( 4%) and of he oal device losses (7%) is achieved. Because he speed of a classical DSP is no suiable o implemen he proposed quasi-analog curren conrol a FPGA has been used o conrol a kw prooype converer. Simulaion and he experimenal resuls show he feasibiliy of he proposed approach.

5 Ac main curren [A] - - (a) Ac main curren [A] - - (a) Main PFC curren [A] Main PFC curren [A] Filering PFC curren [A]..... (c) Fig.. Experimenal resuls - ac main curren(a), main PFC curren, filering PFC curren (c) obained wih a main hyseresis band of. A. Filering PFC curren [A].... (c) Fig.. Experimenal resuls - ac main curren curren(a), main PFC curren, filering PFC curren (c) obained wih a main hyseresis band of. A. Main and Filering PFC curren [A] filering curren main curren Fig. 4. Experimenal resuls - daail of main PFC curren and filering PFC curren (c) obained wih a main hyseresis band of. A. (a) (d) Fig. 6. Experimenal resuls - oscilloscope screen sho of main PFC curren (a); filering PFC curren ; ac line curren (c); oal PFC curren (d). (c)

6 (a) (a) Device emperaure[ o C] ime[min] Fig. 7. Experimenal resuls - hermal image of he esed circui working in single boos mode (a); device emperaure ransien. Device losses[w] Device emperaure[ o C] Fig. 9. Experimenal resuls: device hermal characerisic. filering swich main swich Device losses[w] Device curren[a] Fig. 8. Experimenal resuls - hermal image of he esed circui working in dual boos mode. REFERENCES [] M. Fu and Q. Chen, A DSP based conroller for power facor correcion in a recifier circui, in Proc. 6h Annu. IEEE Applied Power Elecronics Conf. Expo,, pp [] S.Buso e al., Simple digial conrol improving dynamic performance of power facor pre-regulaors, IEEE Trans. Power Elecron., vol., pp. 84 8, Sep [] J. Zhou e al., Novel sampling algorihm for DSP conrolled kw PFC converer, IEEE Trans. Power Elecron., vol. 6, pp. 7, Mar.. [4] S. Bibian and H. Jin, Digial conrol wih improved performance for Boos power facor correcion circuis, in Proc. 6h Annu. IEEE Applied Power Elecronics Conf. Expo,, pp [] S. Kim and P. N. Enjei, Conrol of muliple single phase PFC modules wih a single low-cos DSP, in Proc. 8h Annu. IEEE Applied Power Elecronics Conf. Expo, vol.,, pp [6] J. Chen, A. Prodic, R. W. Erickson, and D. Maksimovic, Predicive digial curren programmed conrol, IEEE Trans. Power Elecron., vol. 8, pp. 4 49, Jan.. [7] A. H. Miwalli, S. B. Leeb, G. C. Verghese, and V. J. Thouvelil, An adapive digial conroller for a uniy power facor converer, IEEE Trans. Power Elecron., vol., pp. 74 8, Mar [8] P. Zumel, A. de Casro, O. Gaecia, T. Riesgo, and J. Uceda, Concurren and simple digial conroller of an ac/dc converer wih power facor correcion, in Proc. IEEE Applied Power Elecronics Conf. Expo,, pp Fig.. Experimenal resuls: device conducion losses. [9] A. de Casro, P. Zumel, O. Gaecia, T. Riesgo, and J. Uceda, Concurren and simple digial conroller of an ac/dc converer wih power facor correcion based on FPGA, IEEE Trans. Power Elecron., vol. 8, pp. 4 4, Jan.. [] I. W. Merfer, Sored-duy-raio conrol for power facor correcion, in Proc. IEEE AppliedPower Elecronics Conf. Expo, vol., 999, pp. 9. [] Igor Merfer Analysis and applicaion of a new conrol mehod for coninuousmode Boos converers in power facor correcion circuis, in Proc.IEEE Power Elecronics Specialiss Conf., vol., 997, pp. 96. [] Y.-F. Liu and P. C. Sen, A general unified large signal model for curren programmed dc-o-dc converers, IEEE Trans. Power Elecron., vol. 9,pp , July 994. [] C. Aaianese, V. Nardi, G. Tomasso Moor Side Acive Filer For High Power Synchronous Drive, Tweny Firs IEEE Applied Power Elecronics Conference (APEC 6), Dallas (USA),9- //6, pp [4] C. Aaianese, V. Nardi, G. Tomasso- Acive Filering For Exploiing Of High Power Synchronous Drives IEEE Inernaional Symposium on Indusrial Elecronics (ISIE) 6, Monreal, Quebec (Canada), 9-/7/6, pp [] C. Aaianese, M. Di Monaco, V. Nardi, G. Tomasso, Moor Side Acive Filer (MSAF). 4h IEEE Indusry Applicaion Annual Meeing (IAS7). /9/7. ISBN/ISSN: [6] C. Aaianese, V. Nardi, G. Tomasso, FPGA Based Conrol Sysem For Moor Side Acive Filer (MSAF). 8h IEEE Power Elecronics Specialiss Conference (PESC7). 7/6/7. (pp. 7-). ISBN/ISSN: [7] N. Mohan, T.M. Undeland, W.P. Robins, Power Elecronics: Converers, Applicaions and Design, John Wiley & Son, 989.