4/4/007 Odd Evn Md Analyi 1/9 Odd/Evn Md Analyi Q: Althugh ymmtric circuit appar t b plntiful in micrwav nginring, it m unlikly that w wuld ftn ncuntr ymmtric urc. D virtual hrt and pn typically vr ccur? A: On wrd uprpitin! f th lmnt f ur circuit ar indpndnt and linar, w can apply uprpitin t analyz ymmtric circuit whn nnymmtric urc ar attachd. Fr xampl, ay w wih t dtrmin th admittanc matrix f thi circuit. W wuld plac a vltag urc at prt 1, and a hrt circuit at prt a t f aymmtric urc if thr vr wa n! 1 1 = =0 Jim Stil Th Univ. f Kana Dpt. f EECS
4/4/007 Odd Evn Md Analyi /9 Hr th rally nat part. W find that th urc n prt 1 can b mdl a tw qual vltag urc in ri, whra th urc at prt can b mdld a tw qual but ppit urc in ri. 0 Thrfr an quivalnt circuit i: Jim Stil Th Univ. f Kana Dpt. f EECS
4/4/007 Odd Evn Md Analyi 3/9 Nw, th abv circuit (du t th urc) i bviuly aymmtric n virtual grund, nr virtual hrt i prnt. But, lt ay w turn ff (i.., t t =0) th bttm urc n ach id f th circuit: Our ymmtry ha bn rtrd! Th ymmtry plan i a virtual pn. Thi circuit i rfrrd t a it vn md, and analyi f it i knwn a th vn md analyi. Th lutin ar knwn a th vn md currnt and vltag! Evaluating th rulting vn md half circuit w find: 1 / 1 = = = 00 400 1 Jim Stil Th Univ. f Kana Dpt. f EECS
4/4/007 Odd Evn Md Analyi 4/9 Nw, lt turn th bttm urc back n but turn ff th tp tw! W nw hav a circuit with dd ymmtry th ymmtry plan i a virtual hrt! Thi circuit i rfrrd t a it dd md, and analyi f it i knwn a th dd md analyi. Th lutin ar knwn a th dd md currnt and vltag! Evaluating th rulting dd md half circuit w find: 1 1 = = = 50 100 1 Jim Stil Th Univ. f Kana Dpt. f EECS
4/4/007 Odd Evn Md Analyi 5/9 Q: But what gd i thi vn md and dd md analyi? Aftr all, th urc n prt 1 i 1 =, and th urc n prt i =0. What ar th currnt and fr th urc? A: Rcall that th urc ar th um f th vn and dd md urc: 1 = = = 0 = and thu inc all th dvic in th circuit ar linar w knw frm uprpitin that th currnt and ar imply th um f th dd and vn md currnt! = = 1 1 1 = 1 1 1 = Thu, adding th dd and vn md analyi rult tgthr: Jim Stil Th Univ. f Kana Dpt. f EECS
4/4/007 Odd Evn Md Analyi 6/9 = = 1 1 1 = = 400 100 400 100 3 = = 80 400 And thn th admittanc paramtr fr thi tw prt ntwrk i: 1 1 1 Y11 = = = 80 80 1 = 0 Y 1 = = = 1 = 0 3 1 3 400 400 And frm th ymmtry f th dvic w knw: Y = Y = 11 1 80 Y = Y = 1 1 3 400 Thu, th full admittanc matrix i: 1 3 80 400 Y = 3 1 400 80 Q: What happn if bth urc ar nnzr? Can w u ymmtry thn? Jim Stil Th Univ. f Kana Dpt. f EECS
4/4/007 Odd Evn Md Analyi 7/9 A: Ablutly! Cnidr th prblm blw, whr nithr urc i qual t zr: 1 1 n thi ca w can dfin an vn md and an dd md urc a: = = 1 1 1 = 1 = Jim Stil Th Univ. f Kana Dpt. f EECS
4/4/007 Odd Evn Md Analyi 8/9 W thn can analyz th vn md circuit: And thn th dd md circuit: And thn cmbin th rult in a linar uprpitin! Jim Stil Th Univ. f Kana Dpt. f EECS
4/4/007 Odd Evn Md Analyi 9/9 On final wrd ( prmi!) abut circuit ymmtry and vn/dd md analyi: prcily th am cncpt xit in lctrnic circuit dign! Spcifically, th diffrntial (dd) and cmmn (vn) md analyi f bilatrally ymmtric lctrnic circuit, uch a diffrntial amplifir! Hi! Yu might rmmbr diffrntial and cmmn md analyi frm uch cla a EECS 41 Elctrnic, r handut uch a Diffrntial Md SmallSignal Analyi f BJT Diffrntial Pair BJT Diffrntial Pair Diffrntial Md Cmmn Md Jim Stil Th Univ. f Kana Dpt. f EECS