Hgh Speed 128-bt BCD Archtecture Usng CLA J.S.V.Sa Prasanth 1, Y.Yamn Dev 2 PG Student [VLSI&ES], Dept. of ECE, Swamy Vvekananda Engneerng College, Kalavara, Andhrapradesh, Inda 1 Assstant Professor, Dept. of ECE, Swamy Vvekanada Engneerng College, Kalavara, Andhrapradesh, Inda 2 ABSTRACT: Arthmetc and memory address computaton are performed usng adder operatons. Hence, desgn of adders forms an mportant subset of electronc chp desgn functonalty. BCD numbers play a promnent role n number system. To perform arthmetc operatons on BCD numbers respectve crcut has to be desgned. To perform BCD addton, BCD adders are used. But the drawback wth the BCD adder s low speed n operaton due to delay n propagatng carry output. Ths low speed operaton wll affect the operaton of entre system n whch t s used. As the technology s advancng day by day there s demand for chps wth hgh speed. So to overcome ths drawback, BCD adder usng CLA s proposed n ths paper. The proposed desgn s attempted here to reduce the delay and thereby ncreasng the speed of response. In exstng BCD archtecture, RCA s used to add numbers. The delay of RCA s hgh so t s effectng the speed of adder. So n the proposed desgn, CLA s used nstead of RCA and also a parallel prefx network s to be used to produce the carry outputs for all stages. In ths paper, a BCD adder usng CLA s to be desgned for 8, 16, 32, 6 and 128-bt sze usng VHDL wth the help of ISE Xlnx desgn sute 1.1. The desgned adder wll be functonally verfed by usng ISIM smulator. Later, t wll be syntheszed usng XST syntheszer to get the area (n terms of LUTS) and delay(ns). Fnally, the desgned BCD adders wll be compared wth conventonal BCD adder n terms of delay(ns). KEYWORDS: BCD, RCA, CLA, parallel prefx network, ISE Xlnx desgn sute1.1, ISIM smulator, XST syntheszer I.INTRODUCTION Human bengs have preferred decmal as ther number base for all calculatons done by hand, snce the tme when the man learned to count on hs ten fngers. Ths fact has never changed, although bnary has been selected as the default base for almost all computers due to the storage and the speed effcency of bnary hardware. The success of bnary numbers was ntroduced n 196, by the report of John von Neumann and hs colleagues at the Insttute for Advanced Study [1]. Afterwards, the desgners have preferred bnary computers due to the speed and the smplcty of bnary arthmetc, but nowadays, there s an ncreasng demand for the decmal arthmetc hardware support n fnancal and commercal applcatons. In all arthmetc unts, whether bnary or decmal, an adder s used [2]. Therefore, t s not surprsng that varous addton technques have been nvented up to now, even for the decmal addton, whch s much less popular than the bnary addton BCD s very common n electronc system where a numerc value s to be dsplayed, especally n systems consstng solely of dgtal logc, and not contanng a mcroprocessor. BCD adder s used to perform addton of two BCD numbers. Addton s the mportant arthmetc operaton whch s to be performed by the processor. The speed of the addton operaton nfluences the speed of the processor. So adder performance must be hgh n order to ncrease the performance of processor and also of entre system. Whle performng addton operaton usng BCD adder, there s a delay n propagaton of carry output. Ths delay wll affect the speed of the adder whch n turn affects the speed of the entre system n whch t s used [3], [], [5]. So there s a need to desgn the BCD adder wth less delay n order to ncrease the speed of the operaton. In ths paper, a BCD adder s desgned wth less delay by modfyng the present archtecture. And also the proposed BCD adder wll be compared wth the exstng BCD adder n terms of delay (ns). Copyrght to IJAREEIE DOI:10.15662/IJAREEIE.2016.051000 7817
Ths paper s structured n bref as Follows-Secton II explans about the BCD addton algorthm and Secton III descrbes the structure and workng of conventonal BCD adder (nothng but present exstng BCD adder). Secton IV dscusses about the proposed BCD adder structure by usng CLA. The results are explaned n secton V Fnally, the paper ends wth concluson and future scope. II.BCD ADDITION ALGORITHM BCD or Bnary Coded Decmal s the number system whch has the bnary numbers or dgts to represent decmal number. A decmal number contans 10 dgts (0-9). Now the equvalent bnary numbers can be found out of these 10 decmal numbers. Lke other number systems BCD operaton may be requred. BCD s a numercal code whch has several rules for addton [6]. The rules are gven below n three steps. Start Enter nputs A, B, C n Convert A, B nto bnary Numbers BCD Addton YES Sum>9 Add correcton Factor 0 or 6 NO Result Fg. 1 Flowchart for BCD addton algorthm If the sum of the two dgts s smaller than 9 there s no carry even though there s a carry If the sum of the two dgts s greater than 9 a correcton s requred Copyrght to IJAREEIE DOI:10.15662/IJAREEIE.2016.051000 7818
If the sum of the two dgts s exactly 9 the nput carry determnes whether a correcton s requred and a carry Output s produced. Fgure 1 represents the algorthm for BCD addton. III.CONVENTIONAL BCD ARCHITECTURE Fgure 3 shows a conventonal BCD adder conssts of -bt bnary adder and carry out crcut. The top module of the - bt bnary adder act as the rpple carry adder.t conssts of seres of full adder. The mddle module of the carryout crcut conssts of OR gate and 2 AND gates. The bottom module of the -bt bnary adder act as rpple carry adder. Rpple Carry adder consst of seres of one half adder and number of full adders. The carryout of one stage s fed drectly to the carry-n of the next stage. Cout s used for the correcton factor. The frst four level BCD adders produce the bnary addton. If the result s greater than 9 a carry output s produced. The result of frst level -bt adder s corrected by addng 6 and also ths carry output s used as carry nput for the next dgt. The 1-bt full adder s the buldng block of all the modules. The output of full adder s sum and carry output. The bnary adder s made up from standard AND and OR gates and allow us to add together sngle bt bnary numbers A and B produce the outputs the sum of the addton and a carry called the carry out (c out bt). The full adder gate level crcut s as shown n fg.3. The frst four level BCD adders produce the bnary addton. If the result s greater than 9 a carry output s produced. The result of frst level -bt adder s corrected by addng 6 and also ths carry output s used as carry nput for the next dgt. A B SUM C n Carry Fg. 2 Full adder The Boolean expresson for S and C o s gven As S A B C C o = AB + BC + AC ABC ABC ABC ABC = The 1-bt full adder s the buldng block of all the modules. The output of full adder s sum and carry output. The bnary adder s made up from standard AND and OR gates and allow us to add together sngle bt bnary numbers A and B produce the outputs the sum of the addton and a carry called the carry out (c out bt). Fgure 2 shows the full adder gate level crcut.the thrd level of CBCD archtecture conssts of a RCA. Ths RCA s used to correct the sum output by addng correcton factor to sum output of frst level RCA. Ths RCA doesn t need any carry nput, so the frst block of ths RCA s a half adder. The half adder can add two numbers and produce sum and carry output. The carry out crcut conssts of two AND gates and one OR gate. The nputs to carry AND gates are sum output of frst level adder. The outputs of AND gates are actng as nput to OR gate. Also the carry output of frst level adder s appled as nput to OR gate. Copyrght to IJAREEIE DOI:10.15662/IJAREEIE.2016.051000 7819
A [127:12] B [127:12] A [7:] B [7:] A [3:0] B [3:0] -bt bnary -bt bnary -bt bnary C n S3 S2 S1 S0 S3 S2 S1 S0 S3 S2 S1 S0 Carry Out -bt bnary -bt bnary -bt bnary S3 S2 S1 S0 S3 S2 S1 S0 S3 S2 S1 S0 Sum [127:12] Sum [7:] Sum [3:0] Fg. 3 Conventonal BCD adders The output of carry out crcut s used carry nput for next BCD dgt addton. Also the carry out crcut output used to generate 1 st and 2 nd bt of correcton factor. The man drawback of n ths archtecture s very slow because of carry propagaton whch affectng the speed of the adder. IV.BCD ADDER USING CLA ARCHITECTURE In order to speed up the BCD adder operaton, a new archtecture s proposed n ths paper. Ths archtecture conssts of CLA, analyzer unt to produce dgt generate and propagate sgnals to form carry network. The carry look ahead adder determnes whether that bt par wll generate a carry or propagate a carry. The carry network s a parallel prefx network [7], [8]. The carry valve for each dgt s computed nsde the carry network by usng below equaton. The network may be parallel prefx or two levels carry look ahead logc and s used for correcton. Output carry = DG+DP.INPUT CARRY. (1) Fgure shows the complete BCD adder ncludng -bt adders for correcton. Correcton s done by addng 0 or 6 to the bnary sum comng from the frst level adder. The correcton step must be fulfllng two requrements. Frst the carry, comng from the prevous dgt should ncrease the bnary sum of the dgt by 1. Second the output carry of the related dgt should determne whether the bnary sum wll be corrected by addng 6 or not. The correcton s requred by addng 6 when there s a decmal carry out whch s comng from the carry network. The combnaton of Carry look ahead adder s cascadng up to 128 bt. When we gve -bt nputs to the crcut t produces DP, DG, sum whch are used as nputs for the carry network. Copyrght to IJAREEIE DOI:10.15662/IJAREEIE.2016.051000 7820
B [127:0] A [127:0] + Analyzer + Carry Network Bnary Bnary Bnary Carry [32] Sum [127:6] Carry [1] Sum[7:] Carry[0] Sum[3:0] C n C out 0 0 0 -Bt Bnary Corrected result [127:6] -Bt Bnary Corrected result [7:] -Bt Bnary Corrected result [3:0] SUM [127:6] SUM [7:] SUM [3:0] Fg. 128-bt BCD usng CLA When correcton s requred the carry nput from the carry network and the nput values gven to the adder and the default value 0 s gven as nputs to the frst stage of the BCD adder usng CLA and f carry produces then the carry from bnary adder agan acts as an nput to the next stage along wth usual nputs. V. RESULT ANALYSIS Fg.1 represents the algorthm for BCD addton, whch s the mportant operaton and performed by the processor. Fg.2 represents Full whch s the mportant buldng block of all the modules. Fg.3 represents conventonal BCD by whch we are formng a carry network. And Fg. Represents the complete BCD adder.these two BCD adder archtectures.e., conventonal BCD adder and BCD adder usng CLA are desgned for 8,16,32,6 and 128 bt nput szes usng VHDL [9]. Functonal smulatons are carred out by usng Xlnx ISIM smulator. The adder desgns are syntheszed usng a Xlnx 1.2[10]. It s a synthess tool from Xlnx. It provdes area report and delay report of the desgn n terms of number of LUTs, slces occuped and n Nano seconds respectvely. Copyrght to IJAREEIE DOI:10.15662/IJAREEIE.2016.051000 7821
Table 1 Comparson of two BCD adders n terms of delay (ns) Input sze Type Delay(ns) Conventonal BCD adder 20.160 8 bt BCD adder usng CLA 18.29 Conventonal BCD adder 30.370 16 bt BCD adder usng CLA 29.62 Conventonal BCD adder 55.72 32 bt 6 bt 128 bt BCD adder usng CLA 50.6 Conventonal BCD adder 106.78 BCD adder usng CLA 93.910 Conventonal BCD adder 207.950 BCD adder usng CLA 172.236 From table 1, t s clear that the BCD adder usng CLA s faster when compared wth the CBCD. As shown n table 1, BCD adder usng CLA for 8, 16, 32, 6 and 128 bt has 1.866 ns,0.908 ns,5.296 ns, 12.568 ns and 35.71 ns delay less respectvely when compared wth CBCD for respectve bt sze. So t can be sad that the desgned BCD adder usng CLA s faster. VI.CONCLUSION In ths paper, BCD adder usng CLA s proposed. The BCD adder usng CLA s desgned for 8, 16, 32, 6 and 128 bt usng VHDL and functonally smulated usng Ism smulator. The desgned adder s syntheszed usng Xlnx 1.2 ISE EDA tool. In order to compare the performance of desgned adder wth the exstng adder, the exstng adder.e., CBCD adder also desgned for the same bt szes usng VHDL, functonally smulated and syntheszed usng same tool mentoned above. Then the desgned adders are compared wth each other n terms of delay (ns). As shown n table 7.1, BCD adder usng CLA for all bt szes has mnmum delay compared to conventonal BCD adder. The BCD adder usng CLA has a delay of 18.29 ns, 29.62 ns, 50.6 ns, 93.910 ns and 172.236 ns for 8, 16, 32, 6 and 128-bt sze respectvely where as CBCD has a delay of 20.160 ns, 30.370 ns, 55.72 ns, 106.78 ns and 207.950 ns for 8, 16, 32, 6 and 128-bt sze respectvely. So BCD adder usng CLA for 8, 16, 32, 6 and 128 bt has 1.866 ns,0.908 ns,5.296 ns, 12.568 ns and 35.71 ns delay less respectvely when compared wth CBCD for respectve bt sze. So t can be concluded that the desgned adder.e., BCD usng CLA s havng less delay when compared to CBCD adder. The BCD adder usng CLA can be used for hgh speed applcatons. VII.FUTURE SCOPE In ths paper a hgh speed BCD adder usng CLA s desgned. So ths adder can be used n the desgn of hgh speed ALUs, computatonal unts and processors. But there s a drawback wth ths adder. The area of adder s ncreasng wth ncrease n the speed of the adder whch n turn ncreases the power consumpton of the adder. So, one can work to decrease the adder area wthout affectng the speed of the adder. REFERENCES [1] A. H. Burks, H. H. Goldsten, and J. von Neumann. Prelmnary Dscusson of thelogcal Desgn of an Electronc Computng Instrument. Techncal report, Insttute foradvanced Study, June 196. [2] M. M. Mano. Dgtal Desgn, pages 129 131. Prentce Hall, thrd edton, 2002. Copyrght to IJAREEIE DOI:10.15662/IJAREEIE.2016.051000 7822
[3] B. Shraz, D. Y. Y. Young, and C. N. Zhang. RBCD: RedundantBnary Coded Decmal. In IEE Proceedngs, Part E, No. 2, volume 136, pages 156 160, March 1989. [] Reduced delay BCD adder, Alp Arslan Bayrakc and Ahmet Akkas ComputerEngneerng Department, Koc Unversty, 2007 IEEE [5] M. F. Cowlshaw. Decmal Floatng-Pont: Algorsm for Computers. In Proceedngs ofieee Symposum on Computer Arthmetc, pages 10 111, June 2003. [6] M. F. Cowlshaw. Decmal Floatng-Pont: Algorsm for Computers. In Proceedngs ofieee Symposum on Computer Arthmetc, pages 10 111, June 2003. [7] J. D. Thompson, N. Karra, and M. J. SchulteB. A 6-Bt Decmal Floatng-Pont. In Proceedngs of the IEEE Computer Socety Annual Symposum on VLSI, pages297 298, February 200. [8] P. M. Kogge and H. S. Stone. A Parallel Algorthm for The Effcent Soluton of ageneral Class of Recurrence Equatons. IEEE Trans. on Computers, C-22(8), Aug. 1973. [9] VHDL prmer by J. Bhaskar [10] Xlnx 1.2 user manual [11] Dgtal desgn Prncples & practces by John F. Wakerly [12] I. S. Hwang. Hgh Speed Bnary and Decmal Arthmetc Unt. Unted States Patent, (,866,656), September 1989. Copyrght to IJAREEIE DOI:10.15662/IJAREEIE.2016.051000 7823