CPE/EE 427, CPE 527 VLSI esign I L21: Sequential Circuits epartment of Electrical and Computer Engineering University of Alabama in Huntsville Aleksandar Milenkovic ( www.ece.uah.edu/~milenka ) www.ece.uah.edu/~milenka/cpe527-5f Review: The Regenerative Property V i1 V o1 V i2 V o2 cascaded inverters V i2 = V o1 A C B If the gain in the transient region is larger than 1, only A and B are stable operation points. C is a metastable operation point. V i1 = V o2 11/7/25 VLSI esign I; A. Milenkovic 2 VLSI esign I; A. Milenkovic 1
Bistable Circuits The cross-coupling of two V i1 inverters results in a bistable circuit (a circuit with two stable states) V i2 Have to be able to change the stored value by making A (or B) temporarily unstable by increasing the loop gain to a value larger than 1 done by applying a trigger pulse at V i1 or V i2 the width of the trigger pulse need be only a little larger than the total propagation delay around the loop circuit (twice the delay of an inverter) Two approaches used cutting the feedback loop (mux based latch) overpowering the feedback loop (as used in SRAMs) 11/7/25 VLSI esign I; A. Milenkovic 3 Review: SR Latch S! S R!! memory 1 1 set R 1 1 1 1 reset disallowed 11/7/25 VLSI esign I; A. Milenkovic 4 VLSI esign I; A. Milenkovic 2
Review: Clocked Latch! Latch clock transparent mode clock clock hold mode 11/7/25 VLSI esign I; A. Milenkovic 5 MUX Based Latches Change the stored value by cutting the feedback loop feedback feedback 1 1 Negative Latch Positive Latch = &! & transparent when the clock is low =! & & transparent when the clock is high 11/7/25 VLSI esign I; A. Milenkovic 6 VLSI esign I; A. Milenkovic 3
TG MUX Based Latch Implementation! input sampled (transparent mode) Latch! feedback (hold mode) 11/7/25 VLSI esign I; A. Milenkovic 7 PT MUX Based Latch Implementation!! Reduced clock load, but threshold drop at output of pass transistors so reduced noise margins and performance 11/7/25 VLSI esign I; A. Milenkovic 8! input sampled (transparent mode) feedback (hold mode) VLSI esign I; A. Milenkovic 4
FF Latch Race Problem Combinational Logic B B B State Registers Which value of B is stored? Two-sided clock constraint T t c-q + t plogic + t su T high < t c-q + t cdlogic 11/7/25 VLSI esign I; A. Milenkovic 9 Master Slave Based ET Flipflop 1 1 M Slave Master clock = transparent hold M = 1 hold transparent 11/7/25 VLSI esign I; A. Milenkovic 1 VLSI esign I; A. Milenkovic 5
Master MS ET Implementation Slave I 2 T 2 I 3 I 5 T 4 I 6 M I 1 T 1 T 3 I 4! 11/7/25 VLSI esign I; A. Milenkovic 11 Master MS ET Implementation Slave I 2 T 2 I 3 M I 5 T 4 I 6 I 1 T 1 T 3 I 4 master transparent slave hold master hold slave transparent! 11/7/25 VLSI esign I; A. Milenkovic 12 VLSI esign I; A. Milenkovic 6
MS ET Timing Properties Assume propagation delays are t pd_inv and t pd_tx, that the contamination delay is, and that the inverter delay to derive! is Set-up time - time before rising edge of that must be valid Propagation delay -time for M to reach Hold time - time must be stable after rising edge of - 11/7/25 VLSI esign I; A. Milenkovic 13 MS ET Timing Properties Assume propagation delays are t pd_inv and t pd_tx, that the contamination delay is, and that the inverter delay to derive! is Set-up time - time before rising edge of that must be valid 3 * t pd_inv + t pd_tx Propagation delay -time for M to reach t pd_inv + t pd_tx Hold time - time must be stable after rising edge of zero 11/7/25 VLSI esign I; A. Milenkovic 14 VLSI esign I; A. Milenkovic 7
Set-up Time Simulation 3 2.5 2 M t setup =.21 ns 1.5 Volts 1.5 -.5 I 2 out.2.4.6.8 1 Time (ns) works correctly 11/7/25 VLSI esign I; A. Milenkovic 15 Set-up Time Simulation 3 2.5 2 I 2 out t setup =.2 ns Volts 1.5 1.5 M -.5.2.4.6.8 1 Time (ns) fails 11/7/25 VLSI esign I; A. Milenkovic 16 VLSI esign I; A. Milenkovic 8
Propagation elay Simulation 3 2.5 2 t c-q(lh) = 16 psec 1.5 Volts 1.5 t c-q(lh) t c-q(hl) t c-q(hl) = 18 psec -.5.5 1 1.5 2 2.5 Time (ns) 11/7/25 VLSI esign I; A. Milenkovic 17 Reduced Load MS ET FF Clock load per register is important since it directly impacts the power dissipation of the clock network. Can reduce the clock load (at the cost of robustness) by making the circuit ratioed! I 1 I 3 T 1 M T2! I 2 I 4 reverse conduction to switch the state of the master, T 1 must be sized to overpower I 2 to avoid reverse conduction, I 4 must be weaker than I 1 11/7/25 VLSI esign I; A. Milenkovic 18 VLSI esign I; A. Milenkovic 9
Non-Ideal Clocks!! Ideal clocks Non-ideal clocks clock skew 1-1 overlap - overlap 11/7/25 VLSI esign I; A. Milenkovic 19 Example of Clock Skew Problems X! P 1 A P 3 I 1 I 2 I 3 I 4! P 2 B P 4! Race condition direct path from to during the short time when both and! are high (1-1 overlap) Undefined state both B and are driving A when and! are both high ynamic storage when and! are both low (- overlap) 11/7/25 VLSI esign I; A. Milenkovic 2 VLSI esign I; A. Milenkovic 1
Pseudostatic Two-Phase ET FF 1 X 2 P 1 A P 3 I 1 I 2 I 3 I 4! P 2 B P 4 master transparent slave hold 1 2 2 t non_overlap dynamic storage 1 master hold slave transparent 11/7/25 VLSI esign I; A. Milenkovic 21 Two Phase Clock Generator A 1 B 2 A B 1 2 11/7/25 VLSI esign I; A. Milenkovic 22 VLSI esign I; A. Milenkovic 11
Power PC Flipflop! 1 1 1!! 11/7/25 VLSI esign I; A. Milenkovic 23 Power PC Flipflop! 1 1 1 1 1! master transparent slave hold master hold slave transparent! 11/7/25 VLSI esign I; A. Milenkovic 24 VLSI esign I; A. Milenkovic 12
Ratioed CMOS Clocked SR Latch! off M2 on M4 1 S M6 M5 off on M1 M3 off M8 M7 on R 1 11/7/25 VLSI esign I; A. Milenkovic 25 Ratioed CMOS Clocked SR Latch off on M2 1! off->on 1 M6 M1 on off S M5 off on off M4 1 off->on M8 1 M3 off on M7 R on 1 11/7/25 VLSI esign I; A. Milenkovic 26 VLSI esign I; A. Milenkovic 13
Sizing Issues 2 1.5 so W/L 5and6 > 3! (Volts) 1.5 2 2.5 3 3.5 4 W/L 5and6 W/L 2and4 = 1.5µm/.25 µm W/L 1and3 =.5µm/.25 µm 11/7/25 VLSI esign I; A. Milenkovic 27 Transient Response 3 SET &! (Volts) 2 1 t c-!! t c-.9 1 1.1 1.2 1.3 1.4 1.5 Time (ns) 11/7/25 VLSI esign I; A. Milenkovic 28 VLSI esign I; A. Milenkovic 14
6 Transistor CMOS SR Latch R S R M5! M2 M4 M6 S M1 M3 11/7/25 VLSI esign I; A. Milenkovic 29 Combinational logic Sequencing output depends on current inputs Sequential logic output depends on current and previous inputs Requires separating previous, current, future Called state or tokens Ex: FSM, pipeline in CL out CL CL Finite State Machine Pipeline 11/7/25 VLSI esign I; A. Milenkovic 3 VLSI esign I; A. Milenkovic 15
Sequencing Cont. If tokens moved through pipeline at constant speed, no sequencing elements would be necessary Ex: fiber-optic cable Light pulses (tokens) are sent down cable Next pulse sent before first reaches end of cable No need for hardware to separate pulses But dispersion sets min time between pulses This is called wave pipelining in circuits In most circuits, dispersion is high elay fast tokens so they don t catch slow ones. 11/7/25 VLSI esign I; A. Milenkovic 31 Sequencing Overhead Use flip-flops to delay fast tokens so they move through exactly one stage each cycle. Inevitably adds some delay to the slow tokens Makes circuit slower than just the logic delay Called sequencing overhead Some people call this clocking overhead But it applies to asynchronous circuits too Inevitable side effect of maintaining sequence 11/7/25 VLSI esign I; A. Milenkovic 32 VLSI esign I; A. Milenkovic 16
Sequential Logic Inputs Combinational Logic Outputs Current State State Registers Next State clock 11/7/25 VLSI esign I; A. Milenkovic 33 Timing Metrics In Out clock clock t su t hold time In data stable t c-q time Out output stable output stable time 11/7/25 VLSI esign I; A. Milenkovic 34 VLSI esign I; A. Milenkovic 17
System Timing Constraints Inputs Combinational Logic Outputs Current State State Registers Next State clock T (clock period) t cdreg + t cdlogic t hold T t c-q + t plogic + t su 11/7/25 VLSI esign I; A. Milenkovic 35 Sequencing Elements Latch: Level sensitive a.k.a. transparent latch, latch Flip-flop: edge triggered A.k.a. master-slave flip-flop, flip-flop, register Timing iagrams Transparent Opaque Edge-trigger Latch Flop (latch) (flop) 11/7/25 VLSI esign I; A. Milenkovic 36 VLSI esign I; A. Milenkovic 18
Latch: Level sensitive Sequencing Elements a.k.a. transparent latch, latch Flip-flop: edge triggered A.k.a. master-slave flip-flop, flip-flop, register Timing iagrams Transparent Opaque Edge-trigger Latch Flop (latch) (flop) 11/7/25 VLSI esign I; A. Milenkovic 37 Latch esign Pass Transistor Latch Pros + + Cons 11/7/25 VLSI esign I; A. Milenkovic 38 VLSI esign I; A. Milenkovic 19
Latch esign Pass Transistor Latch Pros +Tiny + Low clock load Cons V t drop nonrestoring backdriving output noise sensitivity dynamic diffusion input Used in 197 s 11/7/25 VLSI esign I; A. Milenkovic 39 Latch esign Transmission gate + - 11/7/25 VLSI esign I; A. Milenkovic 4 VLSI esign I; A. Milenkovic 2
Latch esign Transmission gate +No V t drop - Requires inverted clock 11/7/25 VLSI esign I; A. Milenkovic 41 Latch esign Inverting buffer + + + Fixes either X 11/7/25 VLSI esign I; A. Milenkovic 42 VLSI esign I; A. Milenkovic 21
Latch esign Inverting buffer + Restoring + No backdriving + Fixes either Output noise sensitivity Or diffusion input Inverted output X 11/7/25 VLSI esign I; A. Milenkovic 43 Latch esign Tristate feedback + X 11/7/25 VLSI esign I; A. Milenkovic 44 VLSI esign I; A. Milenkovic 22
Latch esign Tristate feedback + Static Backdriving risk X Static latches are now essential 11/7/25 VLSI esign I; A. Milenkovic 45 Latch esign Buffered input + + X 11/7/25 VLSI esign I; A. Milenkovic 46 VLSI esign I; A. Milenkovic 23
Latch esign Buffered input + Fixes diffusion input + Noninverting X 11/7/25 VLSI esign I; A. Milenkovic 47 Latch esign Buffered output + X 11/7/25 VLSI esign I; A. Milenkovic 48 VLSI esign I; A. Milenkovic 24
Latch esign Buffered output + No backdriving X Widely used in standard cells + Very robust (most important) - Rather large - Rather slow (1.5 2 FO4 delays) - High clock loading 11/7/25 VLSI esign I; A. Milenkovic 49 Latch esign atapath latch + - X 11/7/25 VLSI esign I; A. Milenkovic 5 VLSI esign I; A. Milenkovic 25
Latch esign atapath latch + Smaller, faster - unbuffered input X 11/7/25 VLSI esign I; A. Milenkovic 51 Flip-Flop esign Flip-flop is built as pair of back-to-back latches X X 11/7/25 VLSI esign I; A. Milenkovic 52 VLSI esign I; A. Milenkovic 26
Enable Enable: ignore clock when en = Mux: increase latch - delay Clock Gating: increase en setup time, skew Symbol Multiplexer esign Clock Gating esign en Latch 1 Latch Latch en en en Flop 1 en Flop Flop en 11/7/25 VLSI esign I; A. Milenkovic 53 Reset Force output low when reset asserted Synchronous vs. asynchronous Symbol Latch Flop reset reset Synchronous Reset Asynchronous Reset reset reset reset reset reset reset 11/7/25 VLSI esign I; A. Milenkovic 54 VLSI esign I; A. Milenkovic 27
Set / Reset Set forces output high when enabled Flip-flop with asynchronous set and reset set reset reset set 11/7/25 VLSI esign I; A. Milenkovic 55 Sequencing Methods Flip-flops T c 2-Phase Latches Pulsed Latches Flip-Flops Flop Combinational Logic Flop 2-Phase Transparent Latches Pulsed Latches 1 2 p 1 2 1 Latch t pw p Latch T c /2 Combinational Logic t nonoverlap Latch Combinational Logic Combinational Logic Half-Cycle 1 Half-Cycle 1 t nonoverlap Latch p Latch 11/7/25 VLSI esign I; A. Milenkovic 56 VLSI esign I; A. Milenkovic 28
Timing iagrams Contamination and Propagation elays A Combinational Logic Y A Y t cd t pd t pd Logic Prop. elay t cd Logic Cont. elay t setup thold t pcq Latch/Flop Clk- Prop elay Flop t ccq t pdq Latch/Flop Clk- Cont. elay Latch - Prop elay t ccq t pcq t pcq t setup t hold Latch - Cont. elay Latch/Flop Setup Time Latch/Flop Hold Time Latch t ccq t pcq t setup t hold t cdq t pdq 11/7/25 VLSI esign I; A. Milenkovic 57 Max-elay: Flip-Flops t ( ) pd Tc 1 42443 sequencing overhead F1 1 Combinational Logic 2 F2 T c t pcq t setup 1 t pd 2 11/7/25 VLSI esign I; A. Milenkovic 58 VLSI esign I; A. Milenkovic 29
Max-elay: Flip-Flops ( setup ) tpd Tc t + tpcq 14243 sequencing overhead F1 1 Combinational Logic 2 F2 T c t pcq t setup 1 t pd 2 11/7/25 VLSI esign I; A. Milenkovic 59 Max elay: 2-Phase Latches ( ) tpd = tpd1+ tpd 2 Tc 1 42443 sequencing overhead 1 2 1 1 1 Combinational 2 2 Combinational 3 Logic 1 Logic 2 L1 L2 L3 3 1 2 T c 1 t pdq1 1 t pd1 2 t pdq2 2 t pd2 3 11/7/25 VLSI esign I; A. Milenkovic 6 VLSI esign I; A. Milenkovic 3
Max elay: 2-Phase Latches ( 2 ) tpd = tpd1+ tpd 2 Tc tpdq 123 sequencing overhead 1 2 1 1 1 Combinational 2 2 Combinational 3 Logic 1 Logic 2 L1 L2 L3 3 1 2 T c 1 t pdq1 1 t pd1 2 t pdq2 2 t pd2 3 11/7/25 VLSI esign I; A. Milenkovic 61 Max elay: Pulsed Latches t pd ( ) Tc max 144 4244443 sequencing overhead 1 p L1 1 Combinational Logic 2 p L2 2 T c 1 t pdq (a) t pw > t setup 1 t pd 2 p (b) t pw < t setup 1 2 t pcq T c t pw tpd tsetup 11/7/25 VLSI esign I; A. Milenkovic 62 VLSI esign I; A. Milenkovic 31
Max elay: Pulsed Latches ( setup ) tpd Tc max tpdq, tpcq + t tpw 14444244443 sequencing overhead 1 p L1 1 Combinational Logic 2 p L2 2 T c 1 t pdq (a) t pw > t setup 1 t pd 2 p (b) t pw < t setup 1 2 t pcq T c t pw tpd tsetup 11/7/25 VLSI esign I; A. Milenkovic 63 Min-elay: Flip-Flops 1 t CL cd F1 2 F2 1 t ccq t cd 2 t hold 11/7/25 VLSI esign I; A. Milenkovic 64 VLSI esign I; A. Milenkovic 32
Min-elay: Flip-Flops 1 t t t CL cd hold ccq F1 2 F2 1 t ccq t cd 2 t hold 11/7/25 VLSI esign I; A. Milenkovic 65 Min-elay: 2-Phase Latches t t cd1, cd 2 1 L1 1 CL Hold time reduced by nonoverlap 2 2 L2 Paradox: hold applies twice each cycle, vs. only once for flops. 1 2 t nonoverlap 1 t ccq t cd But a flop is made of two latches! 2 t hold 11/7/25 VLSI esign I; A. Milenkovic 66 VLSI esign I; A. Milenkovic 33
Min-elay: 2-Phase Latches t t t t t cd1, cd 2 hold ccq nonoverlap 1 L1 1 CL Hold time reduced by nonoverlap 2 2 L2 Paradox: hold applies twice each cycle, vs. only once for flops. 1 2 t nonoverlap 1 t ccq t cd But a flop is made of two latches! 2 t hold 11/7/25 VLSI esign I; A. Milenkovic 67 Min-elay: Pulsed Latches p tcd 1 CL L1 Hold time increased by pulse width 2 p L2 p tpw t hold 1 t ccq t cd 2 11/7/25 VLSI esign I; A. Milenkovic 68 VLSI esign I; A. Milenkovic 34
Min-elay: Pulsed Latches tcd thold tccq + t 1 pw CL p L1 Hold time increased by pulse width 2 p L2 p tpw t hold 1 t ccq t cd 2 11/7/25 VLSI esign I; A. Milenkovic 69 Time Borrowing In a flop-based system: ata launches on one rising edge Must setup before next rising edge If it arrives late, system fails If it arrives early, time is wasted Flops have hard edges In a latch-based system ata can pass through latch while transparent Long cycle of logic can borrow time into next As long as each loop completes in one cycle 11/7/25 VLSI esign I; A. Milenkovic 7 VLSI esign I; A. Milenkovic 35
Time Borrowing Example 1 2 1 1 2 (a) Latch Combinational Logic Latch Combinational Logic Latch Borrowing time across half-cycle boundary Borrowing time across pipeline stage boundary 1 2 (b) Latch Combinational Logic Latch Combinational Logic Loops may borrow time internally but must complete within the cycle 11/7/25 VLSI esign I; A. Milenkovic 71 How Much Borrowing? 2-Phase Latches T borrow c setup + nonoverlap ( ) t t t 2 1 1 2 L1 1 2 Combinational Logic 1 L2 2 1 Pulsed Latches 2 T c t nonoverlap t t t borrow pw setup T c /2 Nominal Half-Cycle 1 elay t borrow t setup 2 11/7/25 VLSI esign I; A. Milenkovic 72 VLSI esign I; A. Milenkovic 36
Clock Skew We have assumed zero clock skew Clocks really have uncertainty in arrival time ecreases maximum propagation delay Increases minimum contamination delay ecreases time borrowing 11/7/25 VLSI esign I; A. Milenkovic 73 Skew: Flip-Flops ( setup skew ) tpd Tc tpcq + t + t 14 424443 t t t + t cd hold sequencing overhead ccq skew F1 1 t pcq 1 Combinational Logic T c t pdq 2 t setup F2 t skew 2 F1 1 CL 2 F2 t skew t hold 1 t ccq 2 t cd 11/7/25 VLSI esign I; A. Milenkovic 74 VLSI esign I; A. Milenkovic 37
Skew: Latches 2-Phase Latches ( 2 ) tpd Tc tpdq 123 sequencing overhead t, t t t t + t cd1 cd 2 hold ccq nonoverlap skew T t t + t + t 2 ( ) c borrow setup nonoverlap skew Pulsed Latches cd hold pw ccq ( setup skew ) tpd Tc max tpdq, tpcq + t tpw + t 1444442444443 t t + t t + t ( ) t t t + t sequencing overhead skew borrow pw setup skew 1 2 1 2 1 1 1 Combinational 2 2 Combinational 3 Logic 1 Logic 2 L1 L2 L3 3 11/7/25 VLSI esign I; A. Milenkovic 75 Two-Phase Clocking If setup times are violated, reduce clock speed If hold times are violated, chip fails at any speed In this class, working chips are most important No tools to analyze clock skew An easy way to guarantee hold times is to use 2- phase latches with big nonoverlap times Call these clocks 1, 2 (ph1, ph2) 11/7/25 VLSI esign I; A. Milenkovic 76 VLSI esign I; A. Milenkovic 38
Safe Flip-Flop In class, use flip-flop with nonoverlapping clocks Very slow nonoverlap adds to setup time But no hold times In industry, use a better timing analyzer Add buffers to slow signals if hold time is at risk 2 1 X 2 1 2 1 2 1 11/7/25 VLSI esign I; A. Milenkovic 77 Summary Flip-Flops: Very easy to use, supported by all tools 2-Phase Transparent Latches: Lots of skew tolerance and time borrowing Pulsed Latches: Fast, some skew tol & borrow, hold time risk 11/7/25 VLSI esign I; A. Milenkovic 78 VLSI esign I; A. Milenkovic 39