CPE/EE 427, CPE 527 VLSI esign I L2: ynamic Sequential Circuits epartment of Electrical and Computer Engineering University of Alabama in Huntsville Aleksandar Milenkovic ( www. ece.uah.edu/~milenka ) www. ece.uah.edu/~milenka/cpe527-3f [Adapted from Rabaey s igital tegrated Circuits, 22, J. Rabaey et al. and Mary Jane Irwin ( www. cse. psu.edu/~mji ) ] Review: Sequential efinitions Static versus dynamic storage static uses a bistable element with feedback (regeneration) and thus preserves its state as long as the power is on static is preferred when updates are infrequent (clock gating) dynamic stores state on parasitic capacitors so only holds the state for a period of time (milliseconds) and requires periodic refresh dynamic is usually simpler (fewer transistors), higher speed, lower power Latch versus flipflop latches arelevel sensitive with two modes: transparent - inputs are passed to and hold - output stable fliplflops are edge sensitive that only sample the inputs on a clock transition /7/23 VLSI esign I; A. Milenkovic 2 Review: Timing Metrics Out clock clock t su t hold time data stable t c-q time Out output stable output stable time /7/23 VLSI esign I; A. Milenkovic 3 VLSI esign I; A. Milenkovic
State Registers Review: System Timing Constraints puts Current State Combinational Logic Outputs Next State clock T (clock period) t cdreg + t cdlogic t hold T t c-q + t plogic + t su /7/23 VLSI esign I; A. Milenkovic 4 ynamic ET Flipflop! master slave T I M T 2 I 2 C C 2! t su = t hold = t c-q =! /7/23 VLSI esign I; A. Milenkovic 5 ynamic ET Flipflop master slave! T I M T 2 I 2 master transparent slave hold C C 2! t su = t pd_tx t hold = zero t c-q = 2 t pd_inv + t pd_tx! master hold slave transparent /7/23 VLSI esign I; A. Milenkovic 6 VLSI esign I; A. Milenkovic 2
ynamic ET FF Race Conditions! T I M T 2 I 2 C C 2!! - overlap race condition t overlap- < t T +t I + t T2 - overlap race condition t overlap- < t hold /7/23 VLSI esign I; A. Milenkovic 7 ynamic Two-Phase ET FF 2 T I M T 2 I 2! C C 2!2 master transparent slave hold 2 t non_overlap master hold slave transparent /7/23 VLSI esign I; A. Milenkovic 8 Pseudostatic ynamic Latch Robustness considerations limit the use of dynamic FF s coupling between signal nets and internal storage nodes can inject significant noise and destroy the FF state leakage currents cause state to leak away with time internal dynamic nodes don t track fluctuations in V that reduces noise margins A simple fix is to make the circuit pseudostatic! Add above logic added to all dynamic latches /7/23 VLSI esign I; A. Milenkovic 9 VLSI esign I; A. Milenkovic 3
C 2 MOS (Clocked CMOS) ET Flipflop A clock-skew insensitive FF Master Slave M 2 M 6! M 4 M C! M 8 M 7 C 2! /7/23 VLSI esign I; A. Milenkovic C 2 MOS (Clocked CMOS) ET Flipflop A clock-skew insensitive FF Master Slave M 2 M 6 M 4 on! on M C! M 8 on M 7 on C 2 master transparent slave hold! master hold slave transparent /7/23 VLSI esign I; A. Milenkovic C 2 MOS FF - Overlap Case Clock-skew insensitive as long as the rise and fall times of the clock edges are sufficiently small M 2 M 6 M 4 M C M 8 C 2!! /7/23 VLSI esign I; A. Milenkovic 2 VLSI esign I; A. Milenkovic 4
Volts C 2 MOS FF - Overlap Case M 2 M 6 M C M 7 C 2!! - overlap constraint t overlap- < t hold /7/23 VLSI esign I; A. Milenkovic 3 C 2 MOS Transient Response 3 2.5 2 M (3) (3) For a. ns clock.5 (.) (.).5 (3) -.5 2 4 6 8 Time (nsec) For a 3 ns clock (race condition exists) /7/23 VLSI esign I; A. Milenkovic 4 Pipelining using C 2 MOS M 2 M 6 M 2! M 4! M 8 M 4 F G Out C M 7 C 2! C 3 NORA Logic What are the constraints on F and G? /7/23 VLSI esign I; A. Milenkovic 5 VLSI esign I; A. Milenkovic 5
Example V V V Number of a static inversions should be even /7/23 VLSI esign I; A. Milenkovic 6 NORA CMOS Modules V V V 2 3 PN PUN Out (a) -module Combinational logic Latch V V V V 4 2 3 PN 4 Out (b) -module /7/23 VLSI esign I; A. Milenkovic 7 True Single Phase Clocked (TSPC) Latches Negative Latch Positive Latch hold when = transparent when = transparent when = hold when = /7/23 VLSI esign I; A. Milenkovic 8 VLSI esign I; A. Milenkovic 6
Embedding Logic in TSPC Latch PUN A B PN A B /7/23 VLSI esign I; A. Milenkovic 9 TSPC ET FF Master Slave M /7/23 VLSI esign I; A. Milenkovic 2 TSPC ET FF Master Slave on on on on M master transparent slave hold master hold slave transparent /7/23 VLSI esign I; A. Milenkovic 2 VLSI esign I; A. Milenkovic 7
Volts Simplified TSPC ET FF M 6 M 9 M 2 X M M 8 M 4 M 7 /7/23 VLSI esign I; A. Milenkovic 22 Simplified TSPC ET FF Mon 6 M 9 M fi fi Mon 2 Xfi! on M 8 M 4 M on 7 fi master transparent slave hold master hold slave transparent /7/23 VLSI esign I; A. Milenkovic 23 Sizing Issues in Simplified TSPC ET FF 3! mod Transistor sizing 2! orig Original width M 4, =.5µm M 7, M 8 = 2µm orig mod.2.4.6.8 Time (nsec) Modified width M 4, = µm M 7, M 8 = µm /7/23 VLSI esign I; A. Milenkovic 24 VLSI esign I; A. Milenkovic 8
Split-Output TSPC Latches Positive Latch Negative Latch A A transparent when = hold when = hold when = transparent when = When =, A = V - V Tn When =, A = V Tp /7/23 VLSI esign I; A. Milenkovic 25 Split-Output TSPC ET FF M /7/23 VLSI esign I; A. Milenkovic 26 Pulsed FF (AM-K6) Pulse registers - a short pulse (glitch clock) is generated locally from the rising (or falling) edge of the system clock and is used as the clock input to the flipflop race conditions are avoided by keeping the transparent mode time very short (during the pulse only) advantage is reduced clock load; disadvantage is substantial increase in verification complexity /Vdd ON/OFF P ON / M ON/ 2 P 2 OFF ON ON OFF /7/23 VLSI esign I; A. Milenkovic 27 X OFF ON OFF Vdd!d P 3 M 4 M OFF 6 ON / VLSI esign I; A. Milenkovic 9
Sense Amp FF (StrongArm SA) Sense amplifier (circuits that accept small swing input signals and amplify them to full rail-to-rail signals) flipflops advantages are reduced clock load and that it can be used as a receiver for reduced swing differential buses M 2 M 9 M 7 M 4! M 6 M 8 /7/23 VLSI esign I; A. Milenkovic 28 Flipflop Comparison Chart Name Type # ld #tr t set -up t hold t pff Mux Static 8 (-!) 2 3t pinv +t ptx t pinv +t ptx PowerPC Static 8 (-!) 6 2-phase Ps-Static 8 (- 2) 6 T-gate ynamic 4 (-!) 8 t ptx t o- 2t pinv +t ptx C 2 MOS ynamic 4 (-!) 8 TSPC ynamic 4 () t pinv t pinv 3t pinv S-O TSPC ynamic 2 () AM K6 ynamic 5 () 9 SA SenseAmp 3 () 2 /7/23 VLSI esign I; A. Milenkovic 29 Choosing a Clocking Strategy Choosing the right clocking scheme affects the functionality, speed, and power of a circuit Two-phase designs + robust and conceptually simple - need to generate and route two clock signals - have to design to accommodate possible skew between the two clock signals Single phase designs + only need to generate and route one clock signal + supported by most automated design methodologies + don t have to worry about skew between the two clocks - have to have guaranteed slopes on the clock edges /7/23 VLSI esign I; A. Milenkovic 3 VLSI esign I; A. Milenkovic