Switch Model of NMOS Transistor V GS Gate CPE/EE 47, CPE 57 VLSI Design I L0: IC Manufacturing Source (of carriers) Drain (of carriers) Department of Electrical and Computer Engineering University of Alabama in Huntsville Open (off) (Gate = 0 ) Closed (on) (Gate = 1 ) Aleksandar Milenkovic ( www. ece.uah.edu/~milenka ) www. ece.uah.edu/~milenka/cpe57-0f [Adapted from Rabaey s Digital Integrated Circuits, 00, J. Rabaey et al.] V GS < V T R on V GS > V T 9//00 VLSI Design I; A. Milenkovic 4 The MOS Transistor Switch Model of PMOS Transistor Polysilicon Aluminum V GS Gate Source (of carriers) Drain (of carriers) Open (off) (Gate = 1 ) Closed (on) (Gate = 0 ) R on V GS > V DD V T V GS < V DD V T 9//00 VLSI Design I; A. Milenkovic 9//00 VLSI Design I; A. Milenkovic 5 The NMOS Transistor Cross Section n areas have been doped with donor ions (arsenic) of concentration N D - electrons are the majority carriers CMOS Inverter: A First Look W Source n+ Polysilicon Gate L p substrate Gate oxide Drain n+ Field-Oxide (SiO ) stopper V in V DD C L V out Bulk (Body) p areas have been doped with acceptor ions (boron) of concentration N A - holes are the majority carriers 9//00 VLSI Design I; A. Milenkovic 9//00 VLSI Design I; A. Milenkovic 6 VLSI Design I; A. Milenkovic 1
CMOS Inverter: Steady State Response Photolithographic Process V DD V DD V OL = 0 V OH = V DD V M = f(r n, R p ) oxidation optical mask R p stepper exposure V out = 1 V out = 0 photoresist removal (ashing) photoresist coating R n photoresist development process step V in = 0 V in = V DD spin, rinse, dry acid etch 9//00 VLSI Design I; A. Milenkovic 7 9//00 VLSI Design I; A. Milenkovic 10 Growing the Silicon Ingot From Smithsonian, 000 9//00 VLSI Design I; A. Milenkovic 8 Patterning - Photolithography 1. Oxidation. Photoresist (PR) coating. Stepper exposure 4. Photoresist development and bake 5. Acid etching Unexposed (negative PR) Exposed (positive PR) 6. Spin, rinse, and dry 7. Processing step Ion implantation Plasma etching Metal deposition 8. Photoresist removal (ashing) SiO mask UV light 9//00 VLSI Design I; A. Milenkovic 11 PR CMOS Process at a Glance Example of Patterning of SiO Define active areas Etch and fill trenches Implant well regions Deposit and pattern polysilicon layer Implant source and drain regions and substrate contacts Create contact and via windows Deposit and pattern metal layers One full photolithography sequence per layer (mask) Built (roughly) from the bottom up 5 metal 4 metal 1 polysilicon exception! source and drain diffusions 1 tubs (akawells, active areas) Silicon base material 1&. After oxidation and deposition of negative photoresist. Stepper exposure Photoresist SiO UV-light Patterned optical mask Exposed resist 5. After etching 8. Final result after removal of resist Chemical or plasma etch Hardened resist SiO 4. After development and etching of resist, chemical or plasma etch of SiO Hardened resist SiO SiO 9//00 VLSI Design I; A. Milenkovic 9 9//00 VLSI Design I; A. Milenkovic 1 VLSI Design I; A. Milenkovic
Diffusion and Ion Implantation 1. Area to be doped is exposed (photolithography). Diffusion or Ion implantation 1. Create thin oxide in the active regions, thick elsewhere. Deposit polysilicon. Etch thin oxide from active region (poly acts as a mask for the diffusion) Self-Aligned Gates 4. Implant dopant 9//00 VLSI Design I; A. Milenkovic 1 9//00 VLSI Design I; A. Milenkovic 16 1. Pattern masking (photolithography) Deposition and Etching cut line Simplified CMOS Inverter Process. Deposit material over entire wafer CVD (Si N 4 ) chemical deposition (polysilicon) sputtering (Al). Etch away unwanted material wet etching dry (plasma) etching p well 9//00 VLSI Design I; A. Milenkovic 14 9//00 VLSI Design I; A. Milenkovic 17 Planarization: Polishing the Wafers P-Well Mask From Smithsonian, 000 9//00 VLSI Design I; A. Milenkovic 15 9//00 VLSI Design I; A. Milenkovic 18 VLSI Design I; A. Milenkovic
Active Mask N+ Select Mask 9//00 VLSI Design I; A. Milenkovic 19 9//00 VLSI Design I; A. Milenkovic Poly Mask Contact Mask 9//00 VLSI Design I; A. Milenkovic 0 9//00 VLSI Design I; A. Milenkovic P+ Select Mask Metal Mask 9//00 VLSI Design I; A. Milenkovic 1 9//00 VLSI Design I; A. Milenkovic 4 VLSI Design I; A. Milenkovic 4
gate oxide A Modern CMOS Process Dual-Well Trench-Isolated CMOS field oxide CMOS Process Walk-Through, con t poly(silicon) After polysilicon deposition and etch Al (Cu) n+ p well p-epi TiSi n well SiO tungsten SiO n+ After n+ source/dram and source/drain implants. These steps also dope the polysilicon. p- SiO After deposition of SiO insulator and contact hole etch 9//00 VLSI Design I; A. Milenkovic 5 9//00 VLSI Design I; A. Milenkovic 8 Modern CMOS Process Walk -Through CMOS Process Walk-Through, con t p-epi Base material: substrate with p- epi layer Al After deposition and patterning of first Al layer. Si N 4 p-epi SiO After deposition of gate- oxide and sacrifical nitride (acts as a buffer layer) Al SiO After plasma etch of insulating trenches using the inverse of the active area mask After deposition of SiO insulator, etching of via s, deposition and patterning of second layer of Al. 9//00 VLSI Design I; A. Milenkovic 6 9//00 VLSI Design I; A. Milenkovic 9 CMOS Process Walk-Through, con t Layout Editor: maxdesign Frame SiO After trench filling, CMP planarization, and removal of sacrificial nitride n After n-well and V Tp adjust implants p After p-well and V Tn adjust implants 9//00 VLSI Design I; A. Milenkovic 7 9//00 VLSI Design I; A. Milenkovic 0 VLSI Design I; A. Milenkovic 5
maxlayer Representation Metals (five) and vias/contacts between the interconnect levels Note that m5 connects only to m4, m4 only to m, etc., and m1only to poly, ndif, and pdif Some technologies support stacked vias Active active areas on/in substrate (poly gates, transistor channels (nfet, pfet ), source and drain diffusions (ndif, pdif ), and well contacts (nwc, pwc)) Wells (nw) and other select areas (pplus, nplus, prb) Design Rule Checker poly_not_fet to all_diff minimum spacing = 0.14 um 9//00 VLSI Design I; A. Milenkovic 1 9//00 VLSI Design I; A. Milenkovic 4 CMOS Inverter maxlayout Out In metal1-poly via metal1 polysilicon metal V DD pfet PMOS (4/.4 = 16/1) pdif NMOS (/.4 = 8/1) metal1-diff via ndif nfet GND metal-metal1 via Design Rules Interface between the circuit designer and process engineer Guidelines for constructing process masks Unit dimension: minimum line width scalable design rules: lambda parameter absolute dimensions: micron rules Rules constructed to ensure that design works even when small fab errors (within some tolerance) occur A complete set includes set of layers intra-layer: relations between objects in the same layer inter-layer: relations between objects on different layers 9//00 VLSI Design I; A. Milenkovic 9//00 VLSI Design I; A. Milenkovic 5 Simplified Layouts in max Online design rule checking (DRC) Automatic fet generation (just overlap poly and diffusion and it creates a transistor) Simplified via/contact generation v1, v, v4, v45 ct, nwc, pwc 0.44 x 0.44 m1 0. x 0. ct Why Have Design Rules? To be able to tolerate some level of fabrication errors such as 1. Mask misalignment. Dust. Process parameters (e.g., lateral diffusion) 0.44 x 0.44 poly 4. Rough surfaces 9//00 VLSI Design I; A. Milenkovic 9//00 VLSI Design I; A. Milenkovic 6 VLSI Design I; A. Milenkovic 6
Intra-Layer Design Rule Origins Transistor Layout Minimum dimensions (e.g., widths) of objects on each layer to maintain that object after fab minimum line width is set by the resolution of the patterning process (photolithography) Minimum spaces between objects (that are not related) on the same layer to ensure they will not short after fab Transistor 1 0.15 0.15 0. micron 0. micron 5 9//00 VLSI Design I; A. Milenkovic 7 9//00 VLSI Design I; A. Milenkovic 40 Intra-Layer Design Rules Select Layer Well Active Select Same Potential 0 or 6 10 Different Potential 9 Contact or Via Hole Polysilicon Metal1 Metal 4 1 5 Select Substrate Well 9//00 VLSI Design I; A. Milenkovic 8 9//00 VLSI Design I; A. Milenkovic 41 Inter-Layer Design Rule Origins Inter-Layer Design Rule Origins, Con t 1. Transistor rules transistor formed by overlap of active and poly layers Transistors Catastrophic error. Contact and via rules M1 contact to p-diffusion M1 contact to n-diffusion M1 contact to poly Mx contact to My Contact Mask Via Masks both materials 0. Contact: 0.44 x 0.44 mask misaligned Unrelated Poly & Diffusion Thinner diffusion, but still working 0.14 9//00 VLSI Design I; A. Milenkovic 9 9//00 VLSI Design I; A. Milenkovic 4 VLSI Design I; A. Milenkovic 7
Vias and Contacts Via 1 Metal to 1 Active Contact 1 Metal to Poly Contact 4 5 9//00 VLSI Design I; A. Milenkovic 4 CMOS Process Layers Mask/Layer name Derivation from drawn layers Alternative names for mask/layer MOSIS mask label n-well =nwell bulk, substrate, tub, n -tub, moat CWN p-well =pwell bulk, substrate, tub, p -tub, moat CWP active =pdiff +ndiff thin oxide, thinox, island, gate oxide CAA polysilicon =poly poly, gate CPG n-diffusion implant =grow(ndiff) ndiff, n -select, nplus, n+ CSN p-diffusion implant =grow(pdiff) pdiff, p -select, pplus, CSP contact =contact contact cut, poly contact, diffusion contact CCP and CCA metal1 =m1 first-level metal CMF metal =m second-level metal CMS via =via metal/metal via CVS metal =m third-level metal CMT glass =glass passivation, overglass, pad COG 9//00 VLSI Design I; A. Milenkovic 44 VLSI Design I; A. Milenkovic 8