THIẾT KẾ VI MẠCH TƯƠNG TỰ CHƯƠNG 2: CMOS Technology

THIẾT KẾ VI MẠCH TƯƠNG TỰ CHƯƠNG 2: CMOS Technology Hoàng Trang-bộ môn Kỹ Thuật Điện Tử hoangtrang@hcmut.edu.vn 1 TP.Hồ Chí Minh 12/2011

1. Overview - IC technology - CMOS vs BJT Hoàng Trang-bộ môn Kỹ Thuật Điện Tử, 12/2011 2

What is Integrated Circuit Technology? Hoàng Trang-bộ môn Kỹ Thuật Điện Tử, 12/2011 3

How Does IC Technology Influence Analog IC Design? Hoàng Trang-bộ môn Kỹ Thuật Điện Tử, 12/2011 4

Classification of Silicon Technology Hoàng Trang-bộ môn Kỹ Thuật Điện Tử, 12/2011 5

Why CMOS Technology? Hoàng Trang-bộ môn Kỹ Thuật Điện Tử, 12/2011 6

Components of a Modern CMOS Technology Hoàng Trang-bộ môn Kỹ Thuật Điện Tử, 12/2011 7

CMOS Components Transistors Hoàng Trang-bộ môn Kỹ Thuật Điện Tử, 12/2011 8

2.BASIC IC PROCESS TECHNOLOGY FUNDAMENTAL IC PROCESSING STEPS 100 200 300 450mm Hoàng Trang-bộ môn Kỹ Thuật Điện Tử, 12/2011 9

Oxidation Hoàng Trang-bộ môn Kỹ Thuật Điện Tử, 12/2011 10

Diffusion Hoàng Trang-bộ môn Kỹ Thuật Điện Tử, 12/2011 11

Ion implantation Hoàng Trang-bộ môn Kỹ Thuật Điện Tử, 12/2011 12

Deposition Hoàng Trang-bộ môn Kỹ Thuật Điện Tử, 12/2011 13

Etching Hoàng Trang-bộ môn Kỹ Thuật Điện Tử, 12/2011 14

Shallow Trench Isolation Hoàng Trang-bộ môn Kỹ Thuật Điện Tử, 12/2011 15

Epitaxial Hoàng Trang-bộ môn Kỹ Thuật Điện Tử, 12/2011 16

Photolithography Hoàng Trang-bộ môn Kỹ Thuật Điện Tử, 12/2011 17

Illustration of Photolithography Exposure Hoàng Trang-bộ môn Kỹ Thuật Điện Tử, 12/2011 18

Illustration of Photolithography Positive Photoresist Hoàng Trang-bộ môn Kỹ Thuật Điện Tử, 12/2011 19

3. TYPICAL DEEP SUBMICRON (DSM) CMOS FABRICATION PROCESS Major Fabrication Steps for a DSM CMOS Process 1)p 1.) p and n wells 2.) Shallow trench isolation 3.) Threshold shift 4.) Thin oxide and gate polysilicon 5.) Lightly doped drains and sources 6.) Sidewall spacer 7.) Heavily doped drains and sources 8.) Siliciding (Salicide and Polycide) 9.) Bottom metal, tungsten plugs, and oxide 10.) Higher level metals, tungsten plugs/vias, and oxide 11.) Top level metal, vias and protective oxide Hoàng Trang-bộ môn Kỹ Thuật Điện Tử, 12/2011 20

3. TYPICAL DEEP SUBMICRON (DSM) CMOS FABRICATION PROCESS Step 1 Starting Material The substrate should be highly doped to act like a good conductor Hoàng Trang-bộ môn Kỹ Thuật Điện Tử, 12/2011 21

3. TYPICAL DEEP SUBMICRON (DSM) CMOS FABRICATION PROCESS Step 2 - n and p wells These are the areas where the transistors will be fabricated - NMOS in the p-well and PMOS in the n-well. Done by implantation followed by a deep diffusion. Hoàng Trang-bộ môn Kỹ Thuật Điện Tử, 12/2011 22

3. TYPICAL DEEP SUBMICRON (DSM) CMOS FABRICATION PROCESS Step 3 Shallow Trench Isolation The shallow trench isolation (STI) electrically isolates one region/transistor from another. Hoàng Trang-bộ môn Kỹ Thuật Điện Tử, 12/2011 23

3. TYPICAL DEEP SUBMICRON (DSM) CMOS FABRICATION PROCESS Step 4 Threshold Shift and Anti-Punch Through Implants - The natural thresholds of the NMOS is about 0V and of the PMOS is about 1.2V. An p-implant p is used to make the NMOS harder to invert and the PMOS easier resulting in threshold voltages balanced around zero volts. - Also an implant can be applied to create a higher-doped region beneath the channels to prevent punch-through from the drain depletion region extending to source depletion region. Hoàng Trang-bộ môn Kỹ Thuật Điện Tử, 12/2011 24

3. TYPICAL DEEP SUBMICRON (DSM) CMOS FABRICATION PROCESS Step 5 Thin Oxide and Polysilicon Gates A thin oxide is deposited followed by polysilicon. These layers are removed where they are not wanted. Hoàng Trang-bộ môn Kỹ Thuật Điện Tử, 12/2011 25

3. TYPICAL DEEP SUBMICRON (DSM) CMOS FABRICATION PROCESS Step 6 Lightly Doped Drains and Sources A lightly-doped implant is used to create a lightly-doped source and drain next to the channel of the MOSFETs. Hoàng Trang-bộ môn Kỹ Thuật Điện Tử, 12/2011 26

3. TYPICAL DEEP SUBMICRON (DSM) CMOS FABRICATION PROCESS Step 7 Sidewall Spacers A layer of dielectric is deposited on the surface and removed in such a way as to leave sidewall spacers next to the thin-oxidepolysilicon-polycide sandwich. These sidewall spacers will prevent the part of the source and drain next to the channel from becoming heavily doped. Hoàng Trang-bộ môn Kỹ Thuật Điện Tử, 12/2011 27

3. TYPICAL DEEP SUBMICRON (DSM) CMOS FABRICATION PROCESS Step 8 Implantation of the Heavily Doped Sources and Drains Note that not only does this step provide the completed sources and drains but allows for ohmic contact into the wells and substrate. Hoàng Trang-bộ môn Kỹ Thuật Điện Tử, 12/2011 28

3. TYPICAL DEEP SUBMICRON (DSM) CMOS FABRICATION PROCESS Step 9 Siliciding Siliciding and polyciding is used to reduce interconnect resistivity by placing a lowresistance silicide such as TiSi2, WSi2, TaSi2, etc. on top of the diffusions. Hoàng Trang-bộ môn Kỹ Thuật Điện Tử, 12/2011 29

3. TYPICAL DEEP SUBMICRON (DSM) CMOS FABRICATION PROCESS Step 10 Intermediate Oxide Layer An oxide layer is used to cover the transistors and to planarize (or polish->cmp) the surface. Hoàng Trang-bộ môn Kỹ Thuật Điện Tử, 12/2011 30

3. TYPICAL DEEP SUBMICRON (DSM) CMOS FABRICATION PROCESS Step 11- First-Level Metal Tungsten plugs are built through the lower intermediate oxide layer to provide contact between the devices, wells and substrate to the first-level metal. Hoàng Trang-bộ môn Kỹ Thuật Điện Tử, 12/2011 31

3. TYPICAL DEEP SUBMICRON (DSM) CMOS FABRICATION PROCESS Step 12 Second-Level Metal The previous step is repeated to from the second-level metal. Hoàng Trang-bộ môn Kỹ Thuật Điện Tử, 12/2011 32

3. TYPICAL DEEP SUBMICRON (DSM) CMOS FABRICATION PROCESS Completed Fabrication After multiple levels of metal are applied, the fabrication is completed with a thicker toplevel metal and a protective layer to hermetically seal the circuit from the environment. Note that metal is used for the upper level metal vias. The chip is electrically connected by removing the protective layer over large bonding pads. Hoàng Trang-bộ môn Kỹ Thuật Điện Tử, 12/2011 33

3. TYPICAL DEEP SUBMICRON (DSM) CMOS FABRICATION PROCESS Scanning Electron Microscope (SEM) of a MOSFET cross-section Hoàng Trang-bộ môn Kỹ Thuật Điện Tử, 12/2011 34

3. TYPICAL DEEP SUBMICRON (DSM) CMOS FABRICATION PROCESS SEM: Showing Metal Levels and Interconnect Hoàng Trang-bộ môn Kỹ Thuật Điện Tử, 12/2011 35

3. TYPICAL DEEP SUBMICRON (DSM) CMOS FABRICATION PROCESS DSM CMOS Technology Summary Hoàng Trang-bộ môn Kỹ Thuật Điện Tử, 12/2011 36

4. ULTRA DEEP SUBMICRON (UDSM) CMOS FABRICATION PROCESS What is UDSM CMOS Technology? Vindication of Moore s Law The minimum feature size decreases by approximately 0.7 every two years. Minimum feature size ~25 nanometers (2012) 2006 state of the art: - 65 nm drawn length - 35 nm transistor gate length - 1.2 nm transistor gate oxide - 8 layers of copper interconnect Hoàng Trang-bộ môn Kỹ Thuật Điện Tử, 12/2011 37

4. ULTRA DEEP SUBMICRON (UDSM) CMOS FABRICATION PROCESS Example: about 65 Nanometer CMOS Technology Hoàng Trang-bộ môn Kỹ Thuật Điện Tử, 12/2011 38

4. ULTRA DEEP SUBMICRON (UDSM) CMOS FABRICATION PROCESS UDSM Metal and Interconnects Hoàng Trang-bộ môn Kỹ Thuật Điện Tử, 12/2011 39

4. ULTRA DEEP SUBMICRON (UDSM) CMOS FABRICATION PROCESS Advantages of UDSM CMOS Technology: Hoàng Trang-bộ môn Kỹ Thuật Điện Tử, 12/2011 40

4. ULTRA DEEP SUBMICRON (UDSM) CMOS FABRICATION PROCESS Disadvantages of UDSM CMOS Technology (for Analog)? Reduction in power supply resulting in reduced headroom Gate leakage currents Reduced d small-signal l intrinsic i i gains Increased nonlinearity (IIP3) Noise and matching? Intrinsic gain and IP3 as a function of the gate overdrive for decreasing VDS: Anne-Johan Annema, et. Al., Analog Circuits in Ultra-Deep-Submicron CMOS, IEEE J. of Solid-State Circuits, 2005 Hoàng Trang-bộ môn Kỹ Thuật Điện Tử, 12/2011 41

4. ULTRA DEEP SUBMICRON (UDSM) CMOS FABRICATION PROCESS the Gate Leakage Problem? Hoàng Trang-bộ môn Kỹ Thuật Điện Tử, 12/2011 42

4. ULTRA DEEP SUBMICRON (UDSM) CMOS FABRICATION PROCESS Gate Leakage and f gate Hoàng Trang-bộ môn Kỹ Thuật Điện Tử, 12/2011 43

4. ULTRA DEEP SUBMICRON (UDSM) CMOS FABRICATION PROCESS UDSM CMOS Technology Summary Increased transconductance and frequency capability Low power supply voltages Reduced parasitics Gate leakage causes challenges for analog applications of UDSM technology Other...? Hoàng Trang-bộ môn Kỹ Thuật Điện Tử, 12/2011 44

5. PN JUNCTIONS in CMOS How are PN Junctions used in CMOS? PN junctions are used to electrically isolate one semiconductor region from another PN diodes Creation of the thermal voltage for bandgap purposes Depletion capacitors voltage variable capacitors (varactors) Components of a PN junction: 1.) p-doped semiconductor a semiconductor having atoms containing a lack of electrons (acceptors). The concentration of acceptors is NA in atoms per cubic centimeter. 2.) n-doped semiconductor a semiconductor having atoms containing an excess of electrons (donors). The concentration of these atoms is ND in atoms per cubic centimeter. Hoàng Trang-bộ môn Kỹ Thuật Điện Tử, 12/2011 45

6. MOS TRANSISTOR PHYSICAL ASPECTS OF MOS TRANSISTORS Physical Structure of MOS Transistors in an n-well Technology Width (W) of the MOSFET = Width of the source/drain diffusion Length (L) of the MOSFET = Width of the polysilicon gate between the S/D diffusions Note: the MOSFET is isolated from the well/substrate by reverse biasing the resulting PN junction Hoàng Trang-bộ môn Kỹ Thuật Điện Tử, 12/2011 46

6. MOS TRANSISTOR PHYSICAL ASPECTS OF MOS TRANSISTORS Enhancement MOSFETs The channel between the source and drain of an enhancement MOSFET is formed when the proper potential is applied to the gate of the MOSFET. This potential inverts the material immediately below the gate to the same type of impurity it as the source and drain forming the channel. Hoàng Trang-bộ môn Kỹ Thuật Điện Tử, 12/2011 47

6. MOS TRANSISTOR PHYSICAL ASPECTS OF MOS TRANSISTORS Depletion Mode MOSFET The channel is diffused into the substrate so that a channel exists between the source and drain with no external gate potential. The threshold voltage for a depletion mode NMOS transistor will be negative (a negative gate potential is necessary to attract enough holes underneath the gate to cause this region to invert to p-type material). Hoàng Trang-bộ môn Kỹ Thuật Điện Tử, 12/2011 48

6. MOS TRANSISTOR PHYSICAL ASPECTS OF MOS TRANSISTORS Weak Inversion Operation Hoàng Trang-bộ môn Kỹ Thuật Điện Tử, 12/2011 49

6. MOS TRANSISTOR LAYOUT OF MOS TRANSISTORS Layout of a Single MOS transistor Comments: Make sure to contact the source and drain with multiple contacts to evenly distribute the current flow under the gate. Minimize the area of the source and drain to reduce bulk-source/drain capacitance. Hoàng Trang-bộ môn Kỹ Thuật Điện Tử, 12/2011 50

6. MOS TRANSISTOR LAYOUT OF MOS TRANSISTORS Geometric Effects Orientation: Devices oriented in the same direction match more precisely than those oriented in other directions Hoàng Trang-bộ môn Kỹ Thuật Điện Tử, 12/2011 51

6. MOS TRANSISTOR LAYOUT OF MOS TRANSISTORS Diffusion and Etch Effects Poly etch rate variation use dummy elements to prevent etch rate differences. Do not put contacts on top of the gate for matched transistors. Be careful of diffusion interactions for diffusions near the channel of the MOSFET Hoàng Trang-bộ môn Kỹ Thuật Điện Tử, 12/2011 52

6. MOS TRANSISTOR LAYOUT OF MOS TRANSISTORS Thermal and Stress Effects Oxide gradients use common centroid geometry layout Stress gradients use proper location and common centroid geometry layout Thermal gradients keep transistors well away from power devices and use common centroid geometry layout with interdigitated transistors Examples of Common Centroid Interdigitated transistor layout: Hoàng Trang-bộ môn Kỹ Thuật Điện Tử, 12/2011 53

6. MOS TRANSISTOR LAYOUT OF MOS TRANSISTORS MOS Transistor Layout Photolithographic invariance (PLI) are transistors that exhibit identical orientation. PLI comes from optical interactions between the UV light and the masks. Examples of the layout of matched MOS transistors: 1. Examples of mirror symmetry and photolithographic invariance. Hoàng Trang-bộ môn Kỹ Thuật Điện Tử, 12/2011 54

6. MOS TRANSISTOR LAYOUT OF MOS TRANSISTORS Examples of the layout of matched MOS transistors (cont) 2. Two transistors sharing a common source and laid out to achieve both photolithographic hi invariance i and common centroid. Hoàng Trang-bộ môn Kỹ Thuật Điện Tử, 12/2011 55

6. MOS TRANSISTOR LAYOUT OF MOS TRANSISTORS Examples of the layout of matched MOS transistors (cont) 3. Compact layout of the previous example. Hoàng Trang-bộ môn Kỹ Thuật Điện Tử, 12/2011 56

7. CAPACITORS in CMOS technology Types of Capacitors for CMOS Technology Hoàng Trang-bộ môn Kỹ Thuật Điện Tử, 12/2011 57

7. CAPACITORS in CMOS technology Characterization of Capacitors Hoàng Trang-bộ môn Kỹ Thuật Điện Tử, 12/2011 58

7. CAPACITORS in CMOS technology PN JUNCTION CAPACITORS PN Junction Capacitors in a Well Hoàng Trang-bộ môn Kỹ Thuật Điện Tử, 12/2011 59

7. CAPACITORS in CMOS technology PN JUNCTION CAPACITORS PN Junction Capacitors in a Well Hoàng Trang-bộ môn Kỹ Thuật Điện Tử, 12/2011 60

7. CAPACITORS in CMOS technology MOSFET GATE CAPACITORS MOSFET Gate Capacitor Structure The MOSFET gate capacitors have the gate as one terminal of the capacitor and some combination of the source, drain, and bulk as the other terminal. In the model of the MOSFET gate capacitor shown below, the gate capacitance is really two capacitors in series depending on the condition of the channel. Hoàng Trang-bộ môn Kỹ Thuật Điện Tử, 12/2011 61

7. CAPACITORS in CMOS technology MOSFET GATE CAPACITORS MOSFET Gate Capacitor Structure The MOSFET gate capacitors have the gate as one terminal of the capacitor and some combination of the source, drain, and bulk as the other terminal. In the model of the MOSFET gate capacitor shown below, the gate capacitance is really two capacitors in series depending on the condition of the channel. Hoàng Trang-bộ môn Kỹ Thuật Điện Tử, 12/2011 62

Reference Phillip E.Allen, Douglas R.Holberg, CMOS Analog Circuit Design, 2 nd Edition, Oxford Univeristy Press, 2002. Hoàng Trang-bộ môn Kỹ Thuật Điện Tử, 12/2011 63