An FPGA based Phased Array Processor for the Sub Millimeter Array
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1 An FPGA based Phased Array Processor for the Sub Millimeter Array Vinayak Nagpal Chalmers University of Technology, Sweden advised by Jonathan Weintroub Smithsonian Astrophysical Observatory Vinayak Nagpal, CTH p. 1/28
2 Outline Introduction: What we plan to build and why? Vinayak Nagpal, CTH p. 2/28
3 Outline Introduction: What we plan to build and why? Infrastructure: What did we have in hand? Vinayak Nagpal, CTH p. 2/28
4 Outline Introduction: What we plan to build and why? Infrastructure: What did we have in hand? Design: How we went around building it? Vinayak Nagpal, CTH p. 2/28
5 Outline Introduction: What we plan to build and why? Infrastructure: What did we have in hand? Design: How we went around building it? Results: Does it work? Vinayak Nagpal, CTH p. 2/28
6 Outline Introduction: What we plan to build and why? Infrastructure: What did we have in hand? Design: How we went around building it? Results: Does it work? Future: Where to go from here? Vinayak Nagpal, CTH p. 2/28
7 Outline Introduction: What we plan to build and why? Infrastructure: What did we have in hand? Design: How we went around building it? Results: Does it work? Future: Where to go from here? Demonstration in M247 for those who want to see it work and discuss in more detail. Vinayak Nagpal, CTH p. 2/28
8 Motivation (VLBI) at 0.8 mm with sufficiently long baselines 20 µas resolution. In sub millimeter electron scattering is reduced. Imaging observation of the event horizon in a black hole e.g. SgrA, M87. Sub-millimeter telescopes: JCMT, CSO, HHT, (ALMA) etc and SMA. SMA full collecting area + JCMT + CSO we need a phased array with interface to standard VLBI recorders, i.e. Mark V. Vinayak Nagpal, CTH p. 3/28
9 Project Objectives Proof of Concept Development time 10 months. INPUT: 8 Antennas (SMA or JCMT/CSO), Single Polarization, 500 MHz Bandwidth. OUTPUT: Real Time Phased Sum of 8 antennas spooled to Mark Vb VLBI data storage unit. Build a scalable system using state of art sampling and FPGA technology. Vinayak Nagpal, CTH p. 4/28
10 Why FPGAs? Field Programmable Gate Arrays Like a PLA but can do much more! FPGA Short development cycle. High cost. Reconfigurable Design can be upgraded ASIC Long cycles Low cost for large volumes. Use or throw. Designs carved in silicon. Vinayak Nagpal, CTH p. 5/28
11 Partners (1) CASPER team at UC Berkeley led by Dan Werthimer building FPGA based radio astronomy signal processing technology. Vinayak Nagpal, CTH p. 6/28
12 Partners (1) CASPER team at UC Berkeley led by Dan Werthimer building FPGA based radio astronomy signal processing technology. (2) MIT/Haystack using (1) to build Digital Back End (DBE) for Mark Vb VLBI storage equipment. Vinayak Nagpal, CTH p. 6/28
13 Partners (1) CASPER team at UC Berkeley led by Dan Werthimer building FPGA based radio astronomy signal processing technology. (2) MIT/Haystack using (1) to build Digital Back End (DBE) for Mark Vb VLBI storage equipment. Let us use (1) combine with (2), customize and build the SMA beam former. Vinayak Nagpal, CTH p. 6/28
14 CASPER Technology ibob Board based on Xilinx Virtex II Pro. Heart of SMA Phased Array Processor Vinayak Nagpal, CTH p. 7/28
15 CASPER Technology ibob Board based on Xilinx Virtex II Pro. Heart of SMA Phased Array Processor iadc boards plug directly into ibobs and provide high speed sampling. Vinayak Nagpal, CTH p. 7/28
16 CASPER Technology ibob Board based on Xilinx Virtex II Pro. Heart of SMA Phased Array Processor iadc boards plug directly into ibobs and provide high speed sampling. Other boards which we didn t need BEE2 CASPER flagship. Vinayak Nagpal, CTH p. 7/28
17 ibob-iadc Atmel ADC (AT84AD001), 2Gsamples/sec or 1Gsample/sec Vinayak Nagpal, CTH p. 8/28
18 ibob-iadc Atmel ADC (AT84AD001), 2Gsamples/sec or 1Gsample/sec Xilinx Virtex II Pro. 5MB SRAM, 50K logic cells, 2 PPC, Rocket I/O Vinayak Nagpal, CTH p. 8/28
19 ibob-iadc Infiniband, VSI, RS-232, 100BaseT Ethernet, External SRAM. Vinayak Nagpal, CTH p. 8/28
20 ibob-iadc Infiniband, VSI, RS-232, 100BaseT Ethernet, External SRAM. Symbolic Representation. Vinayak Nagpal, CTH p. 8/28
21 BEE Design Flow VHDL Low Level Vinayak Nagpal, CTH p. 9/28
22 BEE Design Flow VHDL Low Level Simulink Higher Level Vinayak Nagpal, CTH p. 9/28
23 BEE Design Flow VHDL Low Level Simulink Higher Level Fixed Platform Details hidden in design flow Vinayak Nagpal, CTH p. 9/28
24 BEE Design Flow VHDL Low Level Simulink Higher Level Fixed Platform Details hidden in design flow Berkeley Libraries: Interface, Radio Astronomy Vinayak Nagpal, CTH p. 9/28
25 Mark Vb DBE Time Domain iadc ibob Frequency Domain Analog In From Downconverter ADC 8bits 1024Mhz 4x 8bits 256MHz Fourier Transform 32 point Gain Adjust per bin VSI Bus Interface VLBI Station 1 MarkVb Infiniband Link VSI Mark Vb Recorder ibob Based Mark Vb Re cording Interface Vinayak Nagpal, CTH p. 10/28
26 Single Baseline Phased Array τ φ τ Delay adjust. (Geo,Atm,Inst) f τ Vinayak Nagpal, CTH p. 11/28
27 Single Baseline Phased Array τ τ φ τ f Delay adjust. (Geo,Atm,Inst) Delay and phase adjust. LO LO Mix Mix φ 1 φ 2 φ φ 1 φ 2 f Vinayak Nagpal, CTH p. 11/28
28 Single Baseline Phased Array LO τ φ τ f LO Mix Mix φ φ 2 1 τ φ φ 1 φ 2 Delay adjust. (Geo,Atm,Inst) Delay and phase adjust. Delay and phase adjust with fringe rotation. f Vinayak Nagpal, CTH p. 11/28
29 IF Subsystem M SMA 1 st DCV M Block Filters (MHz) M 0.5 GHz 1.5 GHz f 1 GHz 1024 MHz M MHz f f f Vinayak Nagpal, CTH p. 12/28
30 Phased Array Processor 8 Gbps per antenna Ant 1 Ant 2 Ant 3 Ant 4 ibob-1 VLBI In Ant 5 Ant 6 Ant 7 Ant 8 ibob-2 VSI DBE M5 Recorder Vinayak Nagpal, CTH p. 13/28
31 Phased Array Processor Ant 1 Ant 2 8 Gbps per antenna Ant 3 8 Gbps Ant 4 ibob-1 VLBI In Ant 5 Ant 6 Ant 7 8 Gbps VSI DBE Ant 8 ibob-2 M5 Recorder Vinayak Nagpal, CTH p. 13/28
32 Time Domain Approach Delay τ 1 Delay τ 2 Delay τ 3 Simple Accuracy: τ min << T sample Cannot adjust phase Delay τ n Vinayak Nagpal, CTH p. 14/28
33 Frequency Domain Approach FFT N FFT N FFT N FFT N φ adjust φ adjust φ adjust φ adjust Complex Accuracy: N Large Can adjust phase, hence LO phase compensate and fringe rotation can be done digitally. Vinayak Nagpal, CTH p. 15/28
34 Phased Array Processor iadc 1 PPC Delay Control Antenna 1 Polarization P BPF Chunk Filter BW=480MHz Center=760MHz or Center=1280MHz ADC 8bits 1024Mhz 4x Demux by 4 8bits Digital Delay Line 8bits Accuracy 0.1ns 256MHz 256MHz Delay Control 10bits Average 8bits Antenna 2 Polarization P Antenna 3 Polarization P BPF Chunk Filter BW=480MHz Center=760MHz or Center=1280MHz BPF Chunk Filter BW=480MHz Center=760MHz or Center=1280MHz 8bits ADC 1024Mhz 8bits ADC 1024Mhz 4x Demux by 4 4x Demux by 4 8bits 256MHz 8bits 256MHz Digital Delay Line Accuracy 0.1ns Delay Control Digital Delay Line Accuracy 0.1ns 8bits 256MHz 8bits 256MHz 256MHz 10bits 256MHz 10bits 256MHz Average Average 8bits 8bits XAUI 4x 8bits 1024Mhz To Infiniband connector T s = 0.99ns M Hz τ min = T s ns Delay Control 10bits Average 8bits Antenna 4 Polarization P BPF Chunk Filter BW=480MHz Center=760MHz or Center=1280MHz 8bits ADC 1024Mhz 4x Demux by 4 iadc 2 8bits 256MHz Digital Delay Line Accuracy 0.1ns 8bits 256MHz 256MHz Xilinx Virtex II Pro vp50 Vinayak Nagpal, CTH p. 16/28
35 Coarse Delay DELAY LOGIC RD_PTR Max Delay 4000 ns 8bits WR_PTR Delay Precision 4 ns Control via PPC. CONCAT 32bits FIFO Delay. 4 samples repeat. Delay. 4 sam- DATA ples skipped. Vinayak Nagpal, CTH p. 17/28
36 Fine Delay SELECT DATA bits z 1 z 1 CONCAT 64bit Barrel Selector Arrangement Delay 1 ns Precision Vinayak Nagpal, CTH p. 18/28
37 Super Fine Delay Digital Filter for Delay Magnitude Sample y(n) = x(n D) H i (z) = z ( D) h D (n) = sin π(n D) π(n D) If D is fractional h D (n) becomes a fractional delay filter. FIR approximations of Fractional Delay filters are not symmetrical. Precompute Coefficients for fractional delays from 0.1 ns to 0.9 ns in steps of 0.1 ns. Load coefficients on demand and implement real time FIR filter using 10 taps. Vinayak Nagpal, CTH p. 19/28
38 Super Fine Delay Digital Filter for Delay Magnitude Sample y(n) = x(n D) H i (z) = z ( D) h D (n) = sin π(n D) π(n D) If D is fractional h D (n) becomes a fractional delay filter. FIR approximations of Fractional Delay filters are not symmetrical. Precompute Coefficients for fractional delays from 0.1 ns to 0.9 ns in steps of 0.1 ns. Load coefficients on demand and implement real time FIR filter using 10 taps. Vinayak Nagpal, CTH p. 19/28
39 Super Fine Delay DATA IN z 1 z 1 z 1 z 1 z 1 C 1 C 2 C 3 C 4 C 5 DATA OUT Complex design of demux-by-4 FIR filter 4 Multiplications and 4 partial sums computed in every stage No. of stages = No. of Taps Vinayak Nagpal, CTH p. 20/28
40 Super Fine Delay C 1 C 2 C 3 C 4 C 5 s 9 s 10 s 11 s 12 s 5 s 6 s 7 s 8 s 1 s 2 s 3 s 4 s 5 C 1 s 5 C 2 s 6 s 6 C 1 C 2 s7 C 1 s 7 C 2 s 8 C 1 s 4 C 2 s 5 C 3 s 5 C 4 s 1 s 6 C 3 s 2 C 4 s 2 s 3 s 3 C 3 C 3 s 3 C 4 s 4 s 4 s 4 C 4 C 5 C 5 C 5 C 5 Complex design of demux-by-4 FIR filter 4 Multiplications and 4 partial sums computed in every stage No. of stages = No. of Taps Vinayak Nagpal, CTH p. 20/28
41 It Works too! Mag Mag Sample Channel Sample Channel Sample Average Mag Vinayak Nagpal, CTH p. 21/28
42 It Works too! x 10 6 Correlation Correlation Lag Vinayak Nagpal, CTH p. 21/28
43 It Works too! Channel 0 20 Mag Sample Channel 1 20 Mag Sample Average 20 Mag Sample Vinayak Nagpal, CTH p. 21/28
44 It Works too! x 10 6 Correlation Correlation Lags Vinayak Nagpal, CTH p. 21/28
45 It Works too! x 10 5 Correlation Correlation Lags Vinayak Nagpal, CTH p. 21/28
46 How to get delays? Geometry known well enough. Vinayak Nagpal, CTH p. 22/28
47 How to get delays? Geometry known well enough. Atmosphere need to track Vinayak Nagpal, CTH p. 22/28
48 How to get delays? Geometry known well enough. Atmosphere need to track Noisy Data. Vinayak Nagpal, CTH p. 22/28
49 How to get delays? Geometry known well enough. Atmosphere need to track Noisy Data. SMA Correlator? Vinayak Nagpal, CTH p. 22/28
50 How to get delays? Geometry known well enough. ANT 1 ANT 2 ANT 3 ANT 4 τ 1 τ 2 τ 3 τ 4 SMA CORRELATOR Atmosphere need to track τ 5 τ 6 τ 7 τ 8 SMA PHASED ARRAY PROCESSOR Noisy Data. SMA Correlator? Instrumental different paths. Vinayak Nagpal, CTH p. 22/28
51 How to get delays? Geometry known well enough. ANT 1 ANT 2 ANT 3 ANT 4 τ 1 τ 2 τ 3 τ 4 SMA CORRELATOR Atmosphere need to track τ 5 τ 6 τ 7 τ 8 SMA PHASED ARRAY PROCESSOR Noisy Data. SMA Correlator? Instrumental different paths. Another Correlator? Vinayak Nagpal, CTH p. 22/28
52 What sort of Correlator? 7 Delay measurements. Vinayak Nagpal, CTH p. 23/28
53 What sort of Correlator? 7 Delay measurements. δτ is small! Order of few minutes. Vinayak Nagpal, CTH p. 23/28
54 What sort of Correlator? 7 Delay measurements. δτ is small! Order of few minutes. Time Multiplex 7 Measurements. Vinayak Nagpal, CTH p. 23/28
55 What sort of Correlator? 7 Delay measurements. δτ is small! Order of few minutes. Time Multiplex 7 Measurements. Single Baseline Correlator! Vinayak Nagpal, CTH p. 23/28
56 What sort of Correlator? 7 Delay measurements. δτ is small! Order of few minutes. Time Multiplex 7 Measurements. Single Baseline Correlator! Berkeley Library. Vinayak Nagpal, CTH p. 23/28
57 Correlator FX. DATA_IN PFB FFT X Avg RS_232 DATA_OUT DATA_IN PFB FFT CONJ Vinayak Nagpal, CTH p. 24/28
58 Correlator DATA_IN PFB FFT FX. 64 Complex/32 Real Channel X Avg RS_232 DATA_OUT DATA_IN PFB FFT CONJ Vinayak Nagpal, CTH p. 24/28
59 Correlator FX. DATA_IN 64 Complex/32 Real Channel PFB FFT X Avg RS_232 DATA_OUT Use PFB-FFT from CASPER. DATA_IN PFB FFT CONJ Vinayak Nagpal, CTH p. 24/28
60 Correlator FX. DATA_IN 64 Complex/32 Real Channel DATA_IN PFB FFT X Avg RS_232 DATA_OUT Use PFB-FFT from CASPER. Lots of challenges lots of time. PFB FFT CONJ Vinayak Nagpal, CTH p. 24/28
61 Correlator FX. DATA_IN 64 Complex/32 Real Channel DATA_IN PFB PFB FFT FFT CONJ X Avg RS_232 DATA_OUT Use PFB-FFT from CASPER. Lots of challenges lots of time. Full frequency operation. Vinayak Nagpal, CTH p. 24/28
62 Correlator FX. DATA_IN 64 Complex/32 Real Channel DATA_IN PFB PFB FFT FFT CONJ X Avg RS_232 DATA_OUT Use PFB-FFT from CASPER. Lots of challenges lots of time. Full frequency operation. Dynamic Range. Vinayak Nagpal, CTH p. 24/28
63 Correlator FX. DATA_IN 64 Complex/32 Real Channel DATA_IN PFB PFB FFT FFT CONJ X Avg RS_232 DATA_OUT Use PFB-FFT from CASPER. Lots of challenges lots of time. Full frequency operation. Dynamic Range. Sensitivity Vinayak Nagpal, CTH p. 24/28
64 Does it work? Figure 1: Autocorrelation Vinayak Nagpal, CTH p. 25/28
65 Does it work? Figure 2: SNR = 2dB Vinayak Nagpal, CTH p. 25/28
66 Does it work? Figure 3: SNR = 9dB Vinayak Nagpal, CTH p. 25/28
67 Does it work? Figure 4: SNR = 12dB Vinayak Nagpal, CTH p. 25/28
68 Does it work? Figure 5: SNR = 15dB Vinayak Nagpal, CTH p. 25/28
69 Does it work? db MHz Phase MHz Figure 6: No Delay Vinayak Nagpal, CTH p. 25/28
70 Complete Picture 8 Gbps per antenna Ant 1 More work needed! Ant 2 Ant 3 Ant 4 ibob-1 8 Gbps VLBI In Correlator XAUI Link integration DBE interface Correlator Sensitivity Ant 5 Ant 6 Correlator Ant 8 8 Gbps VSI DBE Automatic delay extraction Fringe Rotation Bandwidth ibob-2 M5 Recorder Vinayak Nagpal, CTH p. 26/28
71 Conclusion The SMA Phased Array Processor development has come a long way. Most major blocks are ready and working. Still some work is needed before the system can be ready for a sky observation. Latest trends in FPGA technology and the CASPER paradigm are effective in making development cycle times shorter! Vinayak Nagpal, CTH p. 27/28
72 Acknowledgements SMA Team: Jonathan Weintroub, Bob Wilson, John Test, Taco, Jim Moran, Ray Blundell, Lincoln Greenhill. CASPER Team: Dan Werthimer, Melvyn Wright, Aaron Parsons, Pierre Droz, Henry Chen, Patrick Crescini. MIT/Haystack: Shep Doeleman, Brian Fanous, Alan Rogers, Alan Whitney. Jon Conway: Onsala Space Observatory, Sweden. Xilinx Inc. Synopsys Inc. Vinayak Nagpal, CTH p. 28/28
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