VLSI Design 12. Design Styles

Transcription

1 Pr odu ctiv it y (T r an s./ St a f -M o nt h ) VLSI Design Last module: Floorplanning Sequential circuit design Clock skew This module Custom and semi-custom design Array-based implementations D. Z. Pan 1 The Design Productivity Challenge Logic Transistors per Chip (K),000,000.m 1,000,000.35m 2.5m 0,000,000 1, Logic Transistors/Chip Transistor/Staff Month 58%/Yr. compound Complexity growth rate x 21%/Yr. compound Productivity growth rate A growing gap between design complexity and design productivity ,000,000,000,000 1,000,000 0,000,000 1,000 0 Productivity (Trans./Staff-Month) Source: sematech97 D. Z. Pan 2 A System-on-a-Chip: Example Impact of Implementation Choices Energy Efficiency (in MOPS/mW) 0-00 Hardwired custom -0 Configurable/Parameterizable Domain-specific processor (e.g. DSP) 1- Embedded microprocessor Courtesy: Philips None Somewhat Fully Flexibility flexible flexible (or application scope) D. Z. Pan 3 D. Z. Pan 4 Design Methodology Implementation Choices Digital Circuit Implementation Approaches Custom Semicustom Cell-based Array-based Source: Gajski Design process traverses iteratively between three abstractions: behavior, structure, and geometry More and more automation for each of these steps D. Z. Pan 5 Standard Cells Compiled Cells Macro Cells Pre-diffused (Gate Arrays) Pre-wired (FPGA's) D. Z. Pan 6 D. Z. Pan 1

2 The Custom Approach Transition to Automation and Regular Structures Intel 4004 Intel 4004 ( 71)( Intel 8080 Intel 8085 Intel 8286 Courtesy Intel Courtesy Intel Intel 8486 D. Z. Pan 7 D. Z. Pan 8 Cell-based Design (or standard s) Standard Cell Example Feedthrough Logic Rows of s Functional module (RAM, multiplier, ) Routing channel Routing channel requirements are reduced by presence of more interconnect layers [Brodersen92] D. Z. Pan 9 D. Z. Pan Standard Cell The New Generation Standard Cell - Example Cell-structure hidden under interconnect layers 3-input NAND (from ST Microelectronics): C = Load capacitance T = input rise/fall time D. Z. Pan 11 D. Z. Pan 12 D. Z. Pan 2

3 Automatic Cell Generation MacroModules Initial transistor geometries Placed transistors Routed Compacted Finished (or 8192 bit) SRAM Generated by hard-macro module generator Courtesy Cadabra D. Z. Pan 13 D. Z. Pan 14 Soft MacroModules Intellectual Property (IP) Cores Synopsys DesignCompiler A Protocol Processor for Wireless D. Z. Pan 15 D. Z. Pan 16 Semicustom Design Flow The Design Closure Problem Design Capture Behavioral Design Iteration Pre-Layout Simulation Post-Layout Simulation HDL HDL Logic Logic Synthesis Floorplanning Placement Structural Physical Circuit Circuit Extraction Routing Routing Iterative Removal of Timing Violations (white lines) Tape-out Courtesy Synopsys D. Z. Pan 17 D. Z. Pan 18 D. Z. Pan 3

4 Integrating Synthesis with Physical Design Late-Binding Implementation RTL (Timing) Constraints Physical Synthesis Array-based Macromodules Fixed netlists Netlist with Place-and-Route Info Pre-diffused (Gate Arrays) Pre-wired (FPGA's) Place-and-Route Optimization Artwork D. Z. Pan 19 D. Z. Pan 20 Gate Array Sea-of-gates Sea-of-gate Primitive Cells polysilicon Oxide-isolation rows of uncommitted s V DD metal possible contact Uncommited Cell PMOS PMOS In1 In2 In3 In4 routing channel Committed Cell (4-input NOR) Out Using oxide-isolation Using gate-isolation D. Z. Pan 21 D. Z. Pan 22 Example: Base Cell of Gate-Isolated GA Example: Flip-Flop in Gate-Isolated GA continuous p-diff strip continuous n-diff strip contact for isolator VDD n-well p-well n-diff p-diff poly m1 m2 contact CLK D VDD CLR Q Q From Smith97 From Smith97 D. Z. Pan 23 D. Z. Pan 24 D. Z. Pan 4

5 Sea-of-gates Prewired Arrays Memory Subsystem Random Logic LSI Logic LEA300K (0.6 μm CMOS) Classification of prewired arrays (or fieldprogrammable devices): Based on Programming Technique Fuse-based (program-once) Non-volatile EPROM based RAM based Programmable Logic Style Array-Based Look-up Table Programmable Interconnect Style Channel-routing Mesh networks Courtesy LSI Logic D. Z. Pan 25 D. Z. Pan 26 D. Z. Pan 5