CBC2 performance with switched capacitor DC-DC converter. systems meeting, 12/2/14

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Trevor Hodge
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1 CBC2 performance with switched capacitor DC-DC converter systems meeting, 12/2/14 1

2 reminder of results from CBC1 +2.5V GND 1n can power CBC from single +2.5V supply 1uF DC-DC diff. clock (CMOS) 1 MHz diff. clock to DC-DC circuit DC-DC DC-DC 1.2 GND(D) 1n DC-DC 1.2V feeds VDDD (dig. supply) and VLDOI (LDO I/P) 1.1V LDO O/P VLDOO feeds analogue stages supply VDDA VDDD alternatively can choose not to use the DC-DC powering all GNDs connected together and just power VDDD from 1.2V DC supply LDO GND(A) VDDA 1n bandgap VLDOO VLDOI 1n 2

3 no. of events no. of events no. of events fixed trig., 1.2V random trig., 1.2V fixed trig., DC-DC random trig., DC-DC 4 41 fixed trig., 1.2V random trig., 1.2V fixed trig., DC-DC random trig., DC-DC fixed trig., 1.2V random trig., 1.2V fixed trig., DC-DC random trig., DC-DC 42 a) Cadded = 1.78 pf b) Cadded = 3.78 pf c) Cadded = 5.79 pf 44 comparator threshold VCTH [mv] DCDC effects on S-curves triggering conditions results fixed trig: random trig. always send trigger at same phase w.r.t. 1 MHz DC-DC clock phase trigger at any random time within DC-DC clock cycle no effects at all if CBC powered from 1.2V DC rail (irrespective of triggering conditions) no effects if CBC triggered at fixed time relative to 1 MHz DC-DC clock phase increasing s-curve distortion with external capacitance if CBC triggered with random phase relationship to 1 MHz 3

4 for largest external capacitance 1 systematic study (DC-DC circuit operating) no. of events Cadded = 5.79 pf acquire s-curves with increasing separation between fast reset time and trigger position (25 nsec steps) not all s-curves in same position 2 plotting s-curve mid-point vs vs. trigger position shows repetitive structure S-curve mid-points [mv] VCTH [mv] [mv rms] separation between positive (or negative) shifts = 4 steps = 1 usec = DC-DC period pedestal shift only, no change in shape => intrinsic unaffected magnitude of effect proportional to external capacitance to ground s-curves in top plot colour coded to show which ones correspond to which point in bottom plot trig. pos'n [ 25 ns steps]

5 summary for CBC1 C f fundamental performance of DC-DC circuit itself is good high efficiency for 2:1 step down conversion no significant effect on intrinsic C EXT but switching transients appear to couple to internal chip ground causing pedestal shifts - magnitudes dependent on external capacitance GND EXT v GND INT worth noting: this would likely not be a problem for hybrid pixel chips low sensor capacitance low inductance bump-bond coupling between sensor and chip grounds 5

6 CBC2 C4 layout, 25um pitch, 19 columns x 43 rows DC-DC powering features retained bandgap, LDO for analogue powering, same as prototype improved step-down DC-DC switched capacitor circuit slower switching edges & rad-hard layout design by Stefano Michelis (CERN) bandgap pipeline + buffering bias gen. 254 inputs CWD, offset correction and colleraltion logic 11 mm 254 amplifier/comparator channels interchip signals DC-DC 5 mm interchip LDO signals 6

7 start by looking at power rails on scope chip A use diff probe on capacitors C1/C7 2.5 V in C4/C8 DCDC output voltage ~1.2 C3/C5 LDO out ~1.1 chip B 7

8 probing voltages voltage on 2.5 V storage capacitor DC-DC converter out Volts Volts DC-DC converter out LDO out x LDO out LDO out with 1.2V DC input x time 1 x time efficiency measurement DC powering: 2 chips draw 141 ma from 1.21 V => 171 mw DC-DC powering: 73.2 ma from 2.6V => 19 mw => ~9% efficiency 8

9 effect on experimental study results here performed using module#5 one CNM n-on-p sensor only => half of channels see capacitive load of sensor other half channels unbonded interesting to see differences between bonded and un module powered using either: DC: ~1.2 V supplied to VDDD (digital rail) 1.1 V VDDA derived from VDDD via LDO DC-DC: ~2.6 V supplied to switched cap circuit running at 1 MHz DC-DC supplies ~1.2 V VDDD 1.1 V VDDA derived from VDDD via LDO initial triggering conditions pseudo-random triggered readout (i.e. no fast reset between triggers) 1 MHz DC-DC clock provided by external oscillator (not synchronized to 4 MHz) 9

10 module #5 1

11 effect on events over thresh events over thresh S-curves 11 no sensor DC powered sensor channels DC-DC powered comparator threshold VCTH 14 rms VCTH units DC-DC DC sensor channels no sensor results for chip A here - results for chip B look the same significant increase for DC-DC powering channel no. 11

12 study more systematically synchronize 1 MHz DC-DC clock with 4 MHz include fast reset in trigger sequence look at s-curve dependence on fast reset - trigger separation increase separation in 25 ns steps (, 1, 2, 3, 43, 44, 45) to cover complete 1 MHz period starting separation fast reset 1 MHz t r I g g e r

systematic s-curve study - chip A 9 18 27 36 13 * 1 1 19 28 37 2 11 2 29 38 * 3 12 21

13 systematic s-curve study - chip A * * * * * * * *

14 systematic s-curve study - chip B * * * * * * * *

15 explanatory key to following 44! slides s-curve mid-points 25ns step value CBC2A CBC2B CBC2A CBC2B CBC2A CBC2B CBC2A CBC2B CBC1 results suggest to look for systematic pedestal shifts - can see that from s-curve mid-point plots in 4 leftmost panels 4 rightmost panels show calculated from s-curves 15

16 s-curve mid-points 1 16

17 s-curve mid-points 2 17

18 s-curve mid-points 3 notice common-mode pedestal shifts 18

19 s-curve mid-points 4 notice common-mode pedestal shifts 19

20 s-curve mid-points 5 notice common-mode pedestal shifts 2

21 s-curve mid-points 6 21

22 s-curve mid-points 7 22

23 s-curve mid-points 8 23

24 s-curve mid-points 9 24

25 * s-curve mid-points 1 pedestal shift varies across chip - same shape for both chips 25

26 s-curve mid-points 11 26

27 * s-curve mid-points 12 pedestal shift varies across chip - same shape for both chips 27

28 * s-curve mid-points 13 pedestal shift varies across chip - same shape for both chips 28

29 * s-curve mid-points 14 pedestal shift varies across chip - same shape for both chips 29

30 s-curve mid-points 15 3

31 s-curve mid-points 16 31

32 s-curve mid-points 17 32

33 s-curve mid-points 18 33

34 s-curve mid-points 19 34

35 s-curve mid-points 2 35

36 s-curve mid-points 21 36

37 s-curve mid-points 22 37

38 s-curve mid-points 23 38

39 s-curve mid-points 24 39

40 s-curve mid-points 25 4

41 s-curve mid-points 26 41

42 s-curve mid-points 27 42

43 s-curve mid-points 28 43

44 s-curve mid-points 29 44

45 * s-curve mid-points 3 pedestal shift varies across chip - same shape for both chips same shape as step 1 (5 nsec previous) 45

46 s-curve mid-points 31 46

47 * s-curve mid-points 32 pedestal shift varies across chip - same shape for both chips same shape as step 12 (5 nsec previous) 47

48 * s-curve mid-points 33 pedestal shift varies across chip - same shape for both chips same shape as step 13 (5 nsec previous) 48

49 * s-curve mid-points 34 pedestal shift varies across chip - same shape for both chips same shape as step 14 (5 nsec previous) 49

50 s-curve mid-points 35 5

51 s-curve mid-points 36 51

52 s-curve mid-points 37 52

53 s-curve mid-points 38 53

54 s-curve mid-points 39 54

55 s-curve mid-points 4 55

56 s-curve mid-points 41 56

57 s-curve mid-points 42 57

58 s-curve mid-points 43 58

59 s-curve mid-points 44 59

60 s-curve mid-points 45 6

61 average s-curve mid-point vs. time step CBC2A CBC2B ~ 1 VCTH units (~ 25 mv) sensor channels sensor channels CBC2A CBC2B ~ 6 VCTH units (~ 15 mv) periodicity of pedestal shift behaviour 5 nsec (1/2 the 1 MHz clock period) amplitude of pedestal movement vs. trigger time depends on whether channel bonded or not 61

62 average vs. time step CBC2A CBC2B 7 reminder of random trigger result 6 DC-DC 5 CBC2A sensor channels CBC2B sensor channels rms VCTH units DC channel no. some variation of intrinsic with time-step (could just be due to non-linearities in VCTH) but dominant extra (with DC-DC powering) coming from pedestal movement 62

63 CBC1:CBC2 comparison 1 no. of events Cadded = 5.79 pf >1 mv CBC2A ~25 mv 2 sensor channels S-curve mid-points [mv] VCTH [mv] [mv rms] CBC2A sensor channels trig. pos'n [ 25 ns steps]

64 summary like CBC1, fundamental performance of DC-DC circuit is good high efficiency for 2:1 step down conversion no significant effect on intrinsic systematic pedestal shift effects remain much smaller in amplitude than for CBC1 characteristic behaviour different pedestal shifts vary ~continuously throughout 1 MHz DC-DC cycle (not just at clock edges) across chip pedestal shift variation at certain phases 64

65 some slides from previous CBC1 talk follow 65

66 CBC performance with switched capacitor DC-DC converter Mark Raymond, Tracker Upgrade Power Working Group, February

67 CBC power features 2 powering features included on CBC prototype pads for test features 2.5 -> 1.25 DC-DC converter LDO regulator (1.2 -> 1.1) feeds analog FE provides stable voltage rail and supply rejection 2.5 -> 1.2 DC-DC converter allows to power CBC using single 2.5 V rail thanks to Michal Bochenek and Federico Faccio for the design and help with incorporating the layout into the CBC 7 mm amplifiers & comparators TEST DEVICES 256 deep pipeline + 32 deep buffers power SLVS data clock trigger I 2 C, reset power LDO bandgap pads for test features 4 mm bias generator 67

68 CBC power features - DC performance 1.25 DC-DC switched capacitor converter DC-DC & LDO outputs converts 2.5 -> ~ 1.2 clearly functioning, high efficiency ~ 9% study of DC-DC switching effects on follows in next slides Volts LDO input LDO output LDO linear regulator provides clean,regulated rail to analog FE ~ 1.2 Vin, 1.1 Vout dropout ~ 4 mv for 6 ma load provides > 3dB supply rejection up to 1 MHz for further details see: CBC_Tracker_Electronics_May_11.pdf 1.5 LDO dropout LDO output [V] us / division 4 mv 1.1 3mA load 6mA load 1.15 LDO input voltage [V]

+2.5V GND 1n 1uF DC-DC DC-DC diff. clock (CMOS) DC-DC 1.2 GND(D) VDDD all GNDs connected together 1n DC-DC powering option can power CBC from single +2.5V supply 1 MHz diff.

69 +2.5V GND 1n 1uF DC-DC DC-DC diff. clock (CMOS) DC-DC 1.2 GND(D) VDDD all GNDs connected together 1n DC-DC powering option can power CBC from single +2.5V supply 1 MHz diff. clock to DC-DC circuit DC-DC 1.2V feeds VDDD (dig. supply) and VLDOI (LDO I/P) 4 external capacitors minimum (actually 5 in this picture) CBC on test board GND +2.5 GND DC-DC 1.2 LDO GND(A) VDDA 1n bandgap VLDOO VLDOI 1n GND GND BGI linked (or not) to BGO maybe don t need this cap 69

70 adding external capacitance want to measure (from s-curves) dependence on external capacitance plug-on boards containing arrays of capacitors connect to bonded out channels acquire s-curve for one of the bonded out channels GND individual channel capacitors GND GND 7

71 no. of events a) Cadded = 1.78 pf s-curves:reference measurement fixed trig., 1.2V b) Cadded = 3.78 pf measure s-curves for single channel for different external capacitances conditions for measurements on this slide no. of events fixed trig., 1.2V digital circuitry supplied with external 1.2 V supply DC-DC not running CBC triggered at fixed time following a fast reset c) Cadded = 5.79 pf => always triggering same pipeline location gives cleanest possible measurement as reference no. of events fixed trig., 1.2V (no reason to expect any effect from random triggering, but just to check) comparator threshold VCTH [mv]

72 no. of events fixed trig., 1.2V random trig., 1.2V 4 41 a) Cadded = 1.78 pf b) Cadded = 3.78 pf 44 s-curves: DC supply (random trigger) now repeat for random triggering digital circuitry still supplied with external 1.2V supply DC-DC still not running but fast reset removed no. of events fixed trig., 1.2V random trig., 1.2V pseudo-random trigger, so now triggering locations throughout pipeline no effect on s-curves visible (i.e. no effect on ) c) Cadded = 5.79 pf (as expected) 8 no. of events fixed trig., 1.2V random trig., 1.2V comparator threshold VCTH [mv]

73 no. of events fixed trig., 1.2V random trig., 1.2V fixed trig., DC-DC 4 41 a) Cadded = 1.78 pf b) Cadded = 3.78 pf 44 s-curves: DC-DC running (fixed trigger time) now feed digital circuitry with DC-DC 1.2 V DC-DC now running return to triggering at fixed time following a fast reset no. of events fixed trig., 1.2V random trig., 1.2V fixed trig., DC-DC DC-DC clocked at 1 MHz with fixed phase relationship to fast reset once again - no significant effect on s-curves c) Cadded = 5.79 pf 44 => DC-DC circuit doesn t affect intrinsic 8 no. of events fixed trig., 1.2V random trig., 1.2V fixed trig., DC-DC comparator threshold VCTH [mv]

74 no. of events no. of events fixed trig., 1.2V random trig., 1.2V fixed trig., DC-DC random trig., DC-DC 4 41 fixed trig., 1.2V random trig., 1.2V fixed trig., DC-DC random trig., DC-DC 4 41 a) Cadded = 1.78 pf b) Cadded = 3.78 pf c) Cadded = 5.79 pf s-curves: DC-DC running (random trigger) now try pseudo-random triggering again DC-DC still running s-curves now distorted for larger capacitance => something to do with random triggering when DC-DC circuit operating an effect associated with specific pipeline locations? try to understand what s going on with a more systematic study => look at s-curve dependence on triggered pipeline location no. of events fixed trig., 1.2V random trig., 1.2V fixed trig., DC-DC random trig., DC-DC comparator threshold VCTH [mv]

75 s-curve dependence on triggered pipeline loc n 1 8 Cadded = 1.78 pf acquire s-curves with increasing separation between fast reset time and trigger position (25 nsec steps) no. of events 6 4 DC-DC circuit operating results here for smallest capacitance: 2 not all s-curves in same position S-curve mid-points [mv] VCTH [mv] 4 steps [mv rms] plotting s-curve mid-point vs vs. trigger position shows repetitive structure separation between positive (or negative) shifts = 4 steps = 1 µsec = DC-DC period pedestal shift only, no change in shape => intrinsic unaffected trig. pos'n [ 25 ns steps]

76 increasing external capacitance 1 8 Cadded = 3.78 pf effect becomes much more noticeable no. of events VCTH [mv] S-curve mid-points [mv] [mv rms] trig. pos'n [ 25 ns steps]

77 for largest external capacitance 1 no. of events Cadded = 5.79 pf s-curves in top plot colour coded to show which ones correspond to which point in bottom plot some distortion visible for most negatively shifted curves (out of amplifier linear range) VCTH [mv] so DC-DC circuit operation somehow affects channel pedestal magnitude of effect proportional to external capacitance to ground S-curve mid-points [mv] [mv rms] trig. pos'n [ 25 ns steps]

78 repeat for external DC supplies 1 just to check no. of events Cadded = 5.8 pf effect goes away completely if DC-DC circuit not operational VCTH [mv] S-curve mid-points [mv] [mv rms] trig. pos'n [ 25 ns steps]

GOLT! RED LIGHT DISTRICT

GOLT! RED LIGHT DISTRICT USER MANUAL v2.1 How RLD Works Signal Flow PROCESSOR The timing processor receives all clock signals and start stop commands. Its main function is to determine which timing signals