CD4008BMS. CMOS 4-Bit Full Adder With Parallel Carry Out. Features. Pinout. Logic Diagram. Applications. Description.

Transcription

1 CD48BMS November 994 CMOS 4-Bit Full Adder With Parallel Carry Out Features Pinout High-Voltage Type (2V Rating) 4 Sum Outputs Plus Parallel Look-ahead Carry-Output CD48BMS TOP VIEW High-Speed Operation - Sum In-To-Sum Out, 6ns Typ; Carry In-To-Carry Out, 5ns Typ. At VDD = V, CL=5pF A4 B VDD B4 Standardized Symmetrical Output Characteristics % Tested For Quiescent Current At 2V A3 B2 A S4 S3 Maximum Input Current of µa at 8V Over Full Package-Temperature Range; B A 6 7 S2 S - na at 8V and 25 o C VSS 8 9 C Noise Margin (Over Full Package Temperature Range): - V at VDD = 5V - 2V at VDD = V - 2.5V at VDD = 5V 5V, V and 5V Parametric Ratings Meets All Requirements of JEDEC Tentative Standard No. 3B, Standard Specifications for Description of B Series CMOS Devices Applications Binary Addition/Arithmetic Units Logic Diagram * 5 B4 * A4 * 2 B3 A3 * 3 HIGH SPEED PAR CARRY 4 (CARRY-OUT) 3 SUM C4 2 SUM S4 S3 Description CD48BMS types consist of four full adder stages with fast look ahead carry provision from stage to stage. Circuitry is included to provide a fast parallel-carry-out but to permit high-speed operation in arithmetic sections using several CD48BMS s. CD48BMS inputs include the four sets of bits to be added, A to A4 and B to B4, in addition to the Carry In bit from a previous section. CD48BMS outputs include the four sum bits, S to S4. In addition to the high speed parallel-carryout which may be utilized at a succeeding CD48BMS section. The CD48BMS is supplied in these 6-lead outline packages: B2 * 4 A2 * 5 * 6 B A * 7 * 9 C (CARRY-IN) VDD = 6 VSS = 8 SUM SUM C3 C2 TRUTH TABLE A i B i C i C O SUM S2 S *ALL INPUTS ARE PROTECTED BY CMOS PROTECTION NETWORK VDD VSS Braze Seal DIP H4T Frit Seal DIP HF Ceramic Flatpack H6W CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures INTERSIL or Copyright Intersil Corporation File Number 3292

2 Specifications CD48BMS Absolute Maximum Ratings DC Supply Voltage Range, (VDD) V to +2V (Voltage Referenced to VSS Terminals) Input Voltage Range, All Inputs V to VDD +.5V DC Input Current, Any One Input ±mA Operating Temperature Range to +25 o C Package Types D, F, K, H Storage Temperature Range (TSTG) o C to +5 o C Lead Temperature (During Soldering) o C At Distance /6 ± /32 Inch (.59mm ±.79mm) from case for s Maximum Reliability Information Thermal Resistance θ ja θ jc Ceramic DIP and FRIT Package o C/W 2 o C/W Flatpack Package o C/W 2 o C/W Maximum Package Power Dissipation (PD) at +25 o C For TA = to + o C (Package Type D, F, K) mW For TA = + o C to +25 o C (Package Type D, F, K).....Derate Linearity at 2mW/ o C to 2mW Device Dissipation per Output Transistor mw For TA = Full Package Temperature Range (All Package Types) Junction Temperature o C TABLE. DC ELECTRICAL PERFORMANCE CHARACTERISTICS GROUP A PARAMETER SYMBOL NDITIONS (NOTE ) SUBGROUPS TEMPERATURE MIN MAX UNITS Supply Current IDD VDD = 2V, VIN = VDD or GND +25 o C - µa o C - µa VDD = 8V, VIN = VDD or GND 3 - µa Input Leakage Current IIL VIN = VDD or GND VDD = o C - - na o C - - na VDD = 8V na Input Leakage Current IIH VIN = VDD or GND VDD = o C - na o C - na VDD = 8V 3 - na Output Voltage VOL5 VDD = 5V, No Load, o C, +25 o C, - 5 mv Output Voltage VOH5 VDD = 5V, No Load (Note 3), o C, +25 o C, V Output Current (Sink) IOL5 VDD = 5V, VOUT =.4V +25 o C.53 - ma Output Current (Sink) IOL VDD = V, VOUT =.5V +25 o C.4 - ma Output Current (Sink) IOL5 VDD = 5V, VOUT =.5V +25 o C ma Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V +25 o C ma Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V +25 o C ma Output Current (Source) IOH VDD = V, VOUT = 9.5V +25 o C ma Output Current (Source) IOH5 VDD = 5V, VOUT = 3.5V +25 o C ma N Threshold Voltage VNTH VDD = V, ISS = -µa +25 o C V P Threshold Voltage VPTH VSS = V, IDD = µa +25 o C V Functional F VDD = 2.8V, VIN = VDD or GND o C VOH > VOL < V VDD = 2V, VIN = VDD or GND o C VDD/2 VDD/2 VDD = 8V, VIN = VDD or GND 8A +25 o C VDD = 3V, VIN = VDD or GND 8B Input Voltage Low (Note 2) VIL VDD = 5V, VOH > 4.5V, VOL <.5V, 2, o C, +25 o C, -.5 V Input Voltage High (Note 2) Input Voltage Low (Note 2) Input Voltage High (Note 2) NOTES: VIH VDD = 5V, VOH > 4.5V, VOL <.5V, 2, o C, +25 o C, V VIL VIH VDD = 5V, VOH > 3.5V, VOL <.5V VDD = 5V, VOH > 3.5V, VOL <.5V. All voltages referenced to device GND, % testing being implemented. 2. Go/No Go test with limits applied to inputs, 2, o C, +25 o C, - 4 V, 2, o C, +25 o C, - V 3. For accuracy, voltage is measured differentially to VDD. Limit is.5v max

3 Specifications CD48BMS TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER SYMBOL NDITIONS (NOTE, 2) Propagation Delay Sum In to Sum Out Propagation Delay Carry In To Cum Out Propagation Delay Sum In To Carry Out Propagation Delay Carry In To Carry Out Transition Time TPHL TPLH TPHL2 TPLH2 TPHL3 TPLH3 TPHL4 TPLH4 GROUP A SUBGROUPS TEMPERATURE MIN MAX UNITS VDD = 5V, VIN = VDD or GND o C - 8 ns, +25 o C, - 8 ns VDD = 5V, VIN = VDD or GND o C - 74 ns, +25 o C, ns VDD = 5V, VIN = VDD or GND o C - 4 ns, +25 o C, - 54 ns VDD = 5V, VIN = VDD or GND o C - 2 ns, +25 o C, - 27 ns TTHL VDD = 5V, VIN = VDD or GND o C - 2 ns TTLH, +25 o C, - 27 ns NOTES:. CL = 5pF, RL = 2K, Input TR, TF < 2ns. 2. and +25 o C limits guaranteed, % testing being implemented. TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER SYMBOL NDITIONS NOTES TEMPERATURE MIN MAX UNITS Supply Current IDD VDD = 5V, VIN = VDD or GND, 2, +25 o C - 5 µa +25 o C - 5 µa VDD = V, VIN = VDD or GND, 2, +25 o C - µa +25 o C - 3 µa VDD = 5V, VIN = VDD or GND, 2, +25 o C - µa +25 o C - 6 µa Output Voltage VOL VDD = 5V, No Load, o C, +25 o C, - 5 mv Output Voltage VOL VDD = V, No Load, o C, +25 o C, Output Voltage VOH VDD = 5V, No Load, o C, +25 o C, Output Voltage VOH VDD = V, No Load, o C, +25 o C, - 5 mv V V Output Current (Sink) IOL5 VDD = 5V, VOUT =.4V, o C.36 - ma.64 - ma Output Current (Sink) IOL VDD = V, VOUT =.5V, o C.9 - ma.6 - ma Output Current (Sink) IOL5 VDD = 5V, VOUT =.5V, o C ma ma Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V, o C ma ma Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V, o C ma ma 7-677

4 Specifications CD48BMS Output Current (Source) IOH VDD = V, VOUT = 9.5V, o C ma ma Output Current (Source) IOH5 VDD =5V, VOUT = 3.5V, o C ma ma Input Voltage Low VIL VDD = V, VOH > 9V, VOL < V, o C, +25 o C, - 3 V Input Voltage High VIH VDD = V, VOH > 9V, VOL < V, o C, +25 o C, Propagation Delay Sum In To Sum Out Propagation Delay Carry In To Sum Out Propagation Delay Sum In To Carry Out Propagation Delay Carry In To Carry Out TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) PARAMETER SYMBOL NDITIONS NOTES TEMPERATURE TPHL TPLH TPHL2 TPLH2 TPLH3 TPHL3 TPHL4 TPLH V VDD = V, 2, o C - 32 ns VDD = 5V, 2, o C - 23 ns VDD = V, 2, o C - 3 ns VDD = 5V, 2, o C - 23 ns VDD = V, 2, o C - 8 ns VDD = 5V, 2, o C - 3 ns VDD = V, 2, o C - ns VDD = 5V, 2, o C - 8 ns Transition Time TTHL VDD = V, 2, o C - ns TTLH VDD = 5V, 2, o C - 8 ns Input Capacitance CIN Any Input, o C pf NOTES:. All voltages referenced to device GND. 2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized on initial design release and upon design changes which would affect these characteristics. 3. CL = 5pF, RL = 2K, Input TR, TF < 2ns. MIN MAX UNITS TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER SYMBOL NDITIONS NOTES TEMPERATURE MIN MAX UNITS Supply Current IDD VDD = 2V, VIN = VDD or GND, o C - 25 µa N Threshold Voltage VNTH VDD = V, ISS = -µa, o C V N Threshold Voltage VNTH VDD = V, ISS = -µa, o C - ± V Delta P Threshold Voltage VPTH VSS = V, IDD = µa, o C V P Threshold Voltage VPTH VSS = V, IDD = µa, o C - ± V Delta Functional F VDD = 8V, VIN = VDD or GND +25 o C VOH > VDD = 3V, VIN = VDD or GND VDD/2 VOL < VDD/2 V 7-678

5 Specifications CD48BMS TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS Propagation Delay Time NOTES: PARAMETER SYMBOL NDITIONS NOTES TEMPERATURE TPHL TPLH. All voltages referenced to device GND. 2. CL = 5pF, RL = 2K, Input TR, TF < 2ns. VDD = 5V, 2, 3, o C -.35 x +25 o C Limit 3. See Table 2 for +25 o C limit. 4. Read and Record MIN MAX UNITS ns TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25 O C PARAMETER SYMBOL DELTA LIMIT Supply Current - MSI-2 IDD ±.µa Output Current (Sink) IOL5 ± 2% x Pre-Test Reading Output Current (Source) IOH5A ± 2% x Pre-Test Reading TABLE 6. APPLICABLE SUBGROUPS NFORMANCE GROUP MIL-STD-883 METHOD GROUP A SUBGROUPS READ AND RERD Initial Test (Pre Burn-In) % 54, 7, 9 IDD, IOL5, IOH5A Interim Test (Post Burn-In) % 54, 7, 9 IDD, IOL5, IOH5A Interim Test 2 (Post Burn-In) % 54, 7, 9 IDD, IOL5, IOH5A PDA (Note ) % 54, 7, 9, Deltas Interim Test 3 (Post Burn-In) % 54, 7, 9 IDD, IOL5, IOH5A PDA (Note ) % 54, 7, 9, Deltas Final Test % 54 2, 3, 8A, 8B,, Group A Sample 55, 2, 3, 7, 8A, 8B, 9,, Group B Subgroup B-5 Sample 55, 2, 3, 7, 8A, 8B, 9,,, Deltas Subgroups, 2, 3, 9,, Subgroup B-6 Sample 55, 7, 9 Group D Sample 55, 2, 3, 8A, 8B, 9 Subgroups, 2 3 NOTE:. 5% Parameteric, 3% Functional; Cumulative for Static and 2. TABLE 7. TOTAL DOSE IRRADIATION MIL-STD-883 TEST READ AND RERD NFORMANCE GROUPS METHOD PRE-IRRAD POST-IRRAD PRE-IRRAD POST-IRRAD Group E Subgroup 2 55, 7, 9 Table 4, 9 Table 4 TABLE 8. BURN-IN AND IRRADIATION TEST NNECTIONS FUNCTION OPEN GROUND VDD 9V ± -.5V Static Burn-In - 4-9, 5 6 Note Static Burn-In 2 Note Dynamic Burn- In Note Irradiation Note , 9, 5, 6 OSCILLATOR 5kHz 25kHz , 4, 6, 5, 3, 5, 7, , 9, 5,

6 Specifications CD48BMS TABLE 8. BURN-IN AND IRRADIATION TEST NNECTIONS OSCILLATOR FUNCTION OPEN GROUND VDD 9V ± -.5V 5kHz 25kHz NOTE:. Each pin except VDD and GND will have a series resistor of K ± 5%, VDD = 8V ±.5V 2. Each pin except VDD and GND will have a series resistor of 47K ± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, failures, VDD = V ±.5V Typical Propagation Delay A3-6 B3-6 CD48 S3-6 2(5) (Ci - ) + (Si - ) + (Ci - SO) = 345 Ci A9-2 B9-2 CD48 S (Ci - ) + (Si - ) + (Ci - SO) Ci A5-8 A5-8 CD48 S (Si - ) + (Ci - SO) = Ci A - 4 B - 4 CD48 S (Si - SO) Ci VSS ALL SUMS SETTLED AFTER 345ns FIGURE. PROPAGATION DELAY FOR A 6 BIT ADDER (V OPERATION) All Intersil semiconductor products are manufactured, assembled and tested under ISO9 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop Melbourne, FL 3292 TEL: (32) FAX: (32) EUROPE Intersil SA Mercure Center, Rue de la Fusee 3 Brussels, Belgium TEL: (32) FAX: (32) ASIA Intersil (Taiwan) Ltd. Taiwan Limited 7F-6, No. Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) FAX: (886)

7 CD48BMS Typical Performance Characteristics SUM-IN TO SUM-OUT PROPAGATION DELAY TIME (tphl, tplh) (ns) SUPPLY VOLTAGE (VDD) = 5V V 5V LOAD CAPACITANCE (CL) (pf) FIGURE 2. TYPICAL SUM-IN TO SUM-OUT PROPAGATION DELAY TIME vs LOAD CAPACITANCE CARRY-IN TO CARRY-OUT PROPAGATION DELAY TIME (tphl, tplh) (ns) SUPPLY VOLTAGE (VDD) = 5V V 5V LOAD CAPACITANCE (CL) (pf) FIGURE 3. TYPICAL CARRY-IN TO CARRY-OUT PROPAGA- TION DELAY TIME vs LOAD CAPACITANCE CARRY-IN TO CARRY-OUT PROPAGATION DELAY TIME (tphl, tplh) (ns) SUPPLY VOLTAGE (VDD) = 5V V 5V SUM-IN TO CARRY-OUT PROPAGATION DELAY TIME (tphl, tplh) (ns) SUPPLY VOLTAGE (VDD) = 5V V 5V LOAD CAPACITANCE (CL) (pf) LOAD CAPACITANCE (CL) (pf) FIGURE 4. TYPICAL CARRY-IN TO SUM-OUT PROPAGATION DELAY TIME vs LOAD CAPACITANCE FIGURE 5. TYPICAL SUM-IN TO CARRY-OUT PROPAGATION DELAY TIME vs LOAD CAPACITANCE DRAIN-TO-SOURCE VOLTAGE (VDS) (V) GATE-TO-SOURCE VOLTAGE (VGS) = -5V -V -5V OUTPUT HIGH (SOURCE) CURRENT (IOH) (ma) DRAIN-TO-SOURCE VOLTAGE (VDS) (V) GATE-TO-SOURCE VOLTAGE (VGS) = -5V -V -5V OUTPUT HIGH (SOURCE) CURRENT (IOH) (ma) FIGURE 6. TYPICAL OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS FIGURE 7. MINIMUM OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS 7-68

8 CD48BMS Typical Performance Characteristics (Continued) OUTPUT LOW (SINK) CURRENT (IOL) (ma) GATE-TO-SOURCE VOLTAGE (VGS) = 5V V 5V OUTPUT LOW (SINK) CURRENT (IOL) (ma) GATE-TO-SOURCE VOLTAGE (VGS) = 5V V 5V 5 5 DRAIN-TO-SOURCE VOLTAGE (VDS) (V) FIGURE 8. TYPICAL OUTPUT LOW (SINK) CURRENT CHARACTERISTICS 5 5 DRAIN-TO-SOURCE VOLTAGE (VDS) (V) FIGURE 9. MINIMUM OUTPUT LOW (SINK) CURRENT CHARACTERISTICS POWER DISSIPATION/PACKAGE (PD) (µw) SUPPLY VOLTAGE (VDD) = 5V V 3.5V INPUT FREQUENCY (fφ) (khz) FIGURE. TYPICAL DISSIPATION CHARACTERISTICS 5V 5V LOAD CAPACITANCE (CL) = 5pF (CL) = 5pF Chip Dimensions and Pad Layouts METALLIZATION: Thickness: kå 4kÅ, AL. PASSIVATION:.4kÅ - 5.6kÅ, Silane BOND PADS:.4 inches X.4 inches MIN DIE THICKNESS:.98 inches -.28 inches Dimensions in parentheses are in millimeters and are derived from the basic inch dimensions as indicated. Grid graduations are in mils ( -3 inch) 7-682