256/512/1K/2K/4K x 9 Asynchronous FIFO

Transcription

1 256/512/1K/2K/4K x 9 Asynchronous FIFO CY7C419/21/25/29/33 256/512/1K/2K/4K x 9 Asynchronous FIFO Features Asynchronous First-In First-Out (FIFO) Buffer Memories 256 x 9 (CY7C419) 512 x 9 (CY7C421) 1K x 9 (CY7C425) 2K x 9 (CY7C429) 4K x 9 (CY7C433) Dual-Ported AM Cell High Speed 50 MHz ead and rite Independent of Depth and idth Low Operating Power: I CC = 35 ma Empty and Full Flags (Half Full Flag in Standalone) TTL Compatible etransmit in Standalone Expandable in idth PLCC, 7x7 TQFP, SOJ, 300-mil, and 600-mil DIP Pb-free Packages Available Pin Compatible and Functionally Equivalent to IDT7200, IDT7201, IDT7202, IDT7203, IDT7204, AM7200, AM7201, AM7202, AM7203, and AM7204 Functional Description The CY7C419, CY7C420/1, CY7C424/5, CY7C428/9, and CY7C432/3 are first-in first-out (FIFO) memories offered in 600-mil wide and 300-mil wide packages. There are 256, 512, 1,024, 2,048, and 4,096 words respectively by 9 bits wide. Each FIFO memory is organized such that the data is read in the same sequential order that it was written. Full and empty flags are provided to prevent overrun and underrun. Three additional pins are also provided to facilitate unlimited expansion in width, depth, or both. The depth expansion technique steers the control signals from one device to another in parallel. This eliminates the serial addition of propagation delays, so that throughput is not reduced. Data is steered in a similar manner. The read and write operations may be asynchronous; each can occur at a rate of 50 MHz. The write operation occurs when the write () signal is LO. ead occurs when read () goes LO. The nine data outputs go to the high impedance state when is HIGH. A Half Full (HF) output flag that is valid in the standalone and width expansion configurations is provided. In the depth expansion configuration, this pin provides the expansion out (XO) information that is used to tell the next FIFO that it is activated. In the standalone and width expansion configurations, a LO on the retransmit (T) input causes the FIFOs to retransmit the data. ead enable () and write enable () must both be HIGH during retransmit, and then is used to access the data. The CY7C419, CY7C420, CY7C421, CY7C424, CY7C425, CY7C428, CY7C429, CY7C432, and CY7C433 are fabricated using an advanced 0.65-micron P-well CMOS technology. Input ESD protection is greater than 2000V and latch up is prevented by careful layout and guard rings. Table 1. Selection Guide 4K x Frequency (MHz) Maximum Access Time (ns) I CC1 (ma) Cypress Semiconductor Corporation 198 Champion Court San Jose, CA Document #: ev. *D evised June 03, 2009

2 Logic Block Diagram DATA INPUTS (D0 D 8) ITE CONTOL ITE POINTE AM AAY 256x 9 512x x x x 9 EAD POINTE THEE- STATE BUES EAD CONTOL DATA OUTPUTS (Q0 Q 8) ESET LOGIC M FL/T FLAG LOGIC XI EXPANSION LOGIC XO/HF Pin Configurations Figure Pin PLCC/LCC (Top View) Figure Pin DIP (Top View) Figure PIn TQFP (Top View) D2 D3 D8 VCC D4 D5 D6 D 2 D 1 D 0 XI Q 0 Q 1 NC Q 2 D D 3 8 NC V cc D 4 D C419 7C421/5/9 7C Q Q GND NC 3 8 Q Q 4 5 D 6 D 7 NC FL/T M XO/HF Q 7 Q 6 D 8 D 3 D 2 D 1 D 0 XI Q 0 Q 1 Q 2 Q 3 Q 8 GND C C420/1 7 7C424/5 8 7C428/9 7C432/ Vcc D 4 D 5 D 6 D 7 FL/T M XO/HF Q 7 Q 6 Q 5 Q 4 D 1 D 0 NC NC XI Q 0 Q C419 7C421/5/9 7C D 7 FL/T NC NC M XO/HF Q 7 Q2 Q3 Q8 GND Q4 Q5 Q6 Document #: ev. *D Page 2 of 16

3 Maximum ating Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested. [1] Storage Temperature C to +150 C Ambient Temperature with Power Applied.. 55 C to +125 C Supply Voltage to Ground Potential V to +7.0V DC Voltage Applied to Outputs in High Z State V to +7.0V DC Input Voltage V to +7.0V Power Dissipation Output Current, into Outputs (LO) ma Static Discharge Voltage... >2000V (per MIL STD 883, Method 3015) Latch Up Current... >200 ma Operating ange ange Ambient Temperature [2] V CC Commercial 0 C to + 70 C 5V ± 10% Industrial 40 C to +85 C 5V ± 10% Electrical Characteristics Over the Operating ange [3] Parameter Description Test Conditions Min All Speed Grades V OH Output HIGH Voltage V CC = Min., I OH = 2.0 ma 2.4 V V OL Output LO Voltage V CC = Min., I OL = 8.0 ma 0.4 V V IH Input HIGH Voltage Commercial 2.0 V CC V Industrial 2.2 V CC V IL Input LO Voltage [4] 0.8 V I IX Input Leakage Current GND < V I < V CC μa I OZ Output Leakage Current > V IH, GND < V O < V CC μa I OS Output Short Circuit Current [5] V CC = Max., V OUT = GND 90 ma Electrical Characteristics Over the Operating ange Parameter Description Test Conditions Min Max Min Max Min Max Min Max Unit I CC Operating Current V CC = Max., Commercial ma I OUT = 0 ma f = f MAX Industrial I CC1 Operating Current V CC = Max., I OUT = 0 ma F = 20 MHz Commercial ma I SB1 Standby Current All Inputs = V IH Min. I SB2 Power Down Current All Inputs > V CC 0.2V Max Unit Commercial ma Industrial Commercial ma Industrial Notes 1. Single Power Supply: The voltage on any input or I/O pin cannot exceed the power pin during power up. 2. T A is the instant on case temperature. 3. See the last page of this specification for Group A subgroup testing information. 4. V IL (Min.) = 2.0V for pulse durations of less than 20 ns. 5. For test purposes, not more than one output at a time should be shorted. Short circuit test duration should not exceed 30 seconds. Document #: ev. *D Page 3 of 16

4 Electrical Characteristics Over the Operating ange [3] Parameter Description Test Conditions Min Max Min Max Min Max Unit I CC Operating Current V CC = Max., Commercial ma I OUT = 0 ma f = f MAX Industrial I CC1 Operating Current V CC = Max., I OUT = 0 ma F = 20 MHz Commercial ma I SB1 Standby Current All Inputs = V IH Min. I SB2 Power Down Current All Inputs > V CC 0.2V Capacitance Tested initially and after any design or process changes that may affect these parameters. Commercial ma Industrial Commercial ma Industrial Parameter Description Test Conditions Max Unit C IN Input Capacitance T A = 25 C, f = 1 MHz, 6 pf C OUT Output Capacitance V CC = 4.5V 6 pf Document #: ev. *D Page 4 of 16

5 Switching Characteristics Over the Operating ange [6, 7] Parameter Description Min Max Min Max Min Max Min Max Unit t C ead Cycle Time ns t A Access Time ns t ead ecovery Time ns t P ead Pulse idth ns t [,8] LZ ead LO to Low Z ns t [8,9] DV Data Valid After ead HIGH ns t [,8,9] HZ ead HIGH to High Z ns t C rite Cycle Time ns t P rite Pulse idth ns t [,8] HZ rite HIGH to Low Z ns t rite ecovery Time ns t SD Data Setup Time ns t HD Data Hold Time ns t MSC M Cycle Time ns t PM M Pulse idth ns t M M ecovery Time ns t P ead HIGH to M HIGH ns t P rite HIGH to M HIGH ns t TC etransmit Cycle Time ns t PT etransmit Pulse idth ns t T etransmit ecovery Time ns t L M to LO ns t HFH M to HF HIGH ns t H M to HIGH ns t ead LO to LO ns t ead HIGH to HIGH ns t rite HIGH to HIGH ns t rite LO to LO ns t HF rite LO to HF LO ns t HF ead HIGH to HF HIGH ns t AE Effective ead from rite HIGH ns t PE Effective ead Pulse idth After HIGH ns t AF Effective rite from ead HIGH ns t PF Effective rite Pulse idth After HIGH ns t XOL Expansion Out LO Delay from Clock ns t XOH Expansion Out HIGH Delay from Clock ns Notes 6. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V and output loading of the specified I OL /I OH and 30 pf load capacitance, as in part (a) of AC Test Load and aveforms, unless otherwise specified. 7. See the last page of this specification for Group A subgroup testing information. 8. t HZ transition is measured at +200 mv from V OL and 200 mv from V OH. t DV transition is measured at the 1.5V level. t HZ and t LZ transition is measured at ±100 mv from the steady state. 9. t HZ and t DV use capacitance loading as in part (b) of AC Test Load and aveforms. Document #: ev. *D Page 5 of 16

6 Switching Characteristics Over the Operating ange [6, 7] (continued) Parameter Description Min Max Min Max Min Max t C ead Cycle Time ns t A Access Time ns t ead ecovery Time ns t P ead Pulse idth ns t LZ [,8] ead LO to Low Z ns t DV [8,9] Data Valid After ead HIGH ns t HZ [,8,9] ead HIGH to High Z ns t C rite Cycle Time ns t P rite Pulse idth ns [,8] t HZ rite HIGH to Low Z ns t rite ecovery Time ns t SD Data Setup Time ns t HD Data Hold Time ns t MSC M Cycle Time ns t PM M Pulse idth ns t M M ecovery Time ns t P ead HIGH to M HIGH ns t P rite HIGH to M HIGH ns t TC etransmit Cycle Time ns t PT etransmit Pulse idth ns t T etransmit ecovery Time ns t L M to LO ns t HFH M to HF HIGH ns t H M to HIGH ns t ead LO to LO ns t ead HIGH to HIGH ns t rite HIGH to HIGH ns t rite LO to LO ns t HF rite LO to HF LO ns t HF ead HIGH to HF HIGH ns t AE Effective ead from rite HIGH ns t PE Effective ead Pulse idth After HIGH ns t AF Effective rite from ead HIGH ns t PF Effective rite Pulse idth After HIGH ns t XOL Expansion Out LO Delay from Clock ns t XOH Expansion Out HIGH Delay from Clock ns Unit Document #: ev. *D Page 6 of 16

7 Switching aveforms Figure 4. Asynchronous ead and rite t C t P t A t t A t LZ t DV t HZ Q 0 Q 8 t P t C t t SD t HD D 0 D 8 M Figure 5. Master eset t [11] MSC t PM [10], t P t L t P t M t HFH HF t H Figure 6. Half-full Flag HALF FULL HALF FULL+1 HALF FULL t HF HF t HF Notes 10. and V IH around the rising edge of M 11. t MSC = t PM + t M. Document #: ev. *D Page 7 of 16

8 Switching aveforms (continued) Figure 7. Last rite to First ead Full Flag LAST ITE FIST EAD ADDITIONAL EADS FIST ITE t t LAST EAD Figure 8. Last ead to First rite Empty Flag FIST ITE ADDITIONAL ITES FIST EAD t t t A DATA OUT VALID VALID t TC [13] Figure 9. etransmit [12] FL/T t PT, t T Notes 12., HF and may change state during retransmit as a result of the offset of the read and write pointers, but flags are valid at t TC. 13. t TC = t PT + t T. Document #: ev. *D Page 8 of 16

9 Switching aveforms (continued) Figure 10. Empty Flag and ead Data Flow-through Mode DATA IN t AE t t PE t t HZ t A DATA OUT Figure 11. Full Flag and rite Data Flow-through Mode t AF t PF t t t HD DATA IN t A t SD DATA OUT Document #: ev. *D Page 9 of 16

10 Switching aveforms (continued) Figure 12. Expansion Timing Diagrams ITE TO LAST PHYSICAL LOCATION OF DEVICE 1 ITE TO FIST PHYSICAL LOCATION OF DEVICE 2 t XO 1 (XI 2 ) [14] t XOL t XOH t HD t SD t SD t HD D 0 D 8 EAD FOM LAST PHYSICAL LOCATION OF DEVICE 1 t EAD FOM FIST PHYSICAL LOCATION OF DEVICE 2 [14] XO 1 (XI 2 ) t XOL t XOH t HZ t LZ t DV t DV Q 0 Q 8 DATA VALID DATA VALID t A t A Note 14. Expansion Out of device 1 (XO 1 ) is connected to Expansion In of device 2 (XI 2 ) Document #: ev. *D Page 10 of 16

11 Architecture The CY7C419, CY7C420/1, CY7C424/5, CY7C428/9, CY7C432/3 FIFOs consist of an array of 256, 512, 1024, 2048, 4096 words of 9 bits each (implemented by an array of dual-port AM cells), a read pointer, a write pointer, control signals (,, XI, XO, FL, T, M), and Full, Half Full, and Empty flags. Dual-Port AM The dual-port AM architecture refers to the basic memory cell used in the AM. The cell itself enables the read and write operations to be independent of each other, which is necessary to achieve truly asynchronous operation of the inputs and outputs. A second benefit is that the time required to increment the read and write pointers is much less than the time required for data propagation through the memory, which is the case if memory is implemented using the conventional register array architecture. esetting the FIFO Upon power up, the FIFO must be reset with a Master eset (M) cycle. This causes the FIFO to enter the empty condition signified by the Empty flag () being LO, and both the Half Full (HF) and Full flags () being HIGH. ead () and write () must be HIGH t P /t P before and t M after the rising edge of M for a valid reset cycle. If reading from the FIFO after a reset cycle is attempted, the outputs are in the high impedance state. riting Data to the FIFO The availability of at least one empty location is indicated by a HIGH. The falling edge of initiates a write cycle. Data appearing at the inputs (D 0 D 8 ) t SD before and t HD after the rising edge of are stored sequentially in the FIFO. The LO-to-HIGH transition occurs t after the first LO-to-HIGH transition of for an empty FIFO. HF goes LO t HF after the falling edge of following the FIFO actually being Half Full. Therefore, the HF is active after the FIFO is filled to half its capacity plus one word. HF remains LO while less than one half of total memory is available for writing. The LO-to-HIGH transition of HF occurs t HF after the rising edge of when the FIFO goes from half full +1 to half full. HF is available in standalone and width expansion modes. goes LO t after the falling edge of, during the cycle in which the last available location is filled. Internal logic prevents overrunning a full FIFO. rites to a full FIFO are ignored and the write pointer is not incremented. goes HIGH t after a read from a full FIFO. eading Data from the FIFO The falling edge of initiates a read cycle if the is not LO. Data outputs (Q 0 to Q 8 ) are in a high impedance condition between read operations ( HIGH), when the FIFO is empty, or when the FIFO is not the active device in the depth expansion mode. hen one word is in the FIFO, the falling edge of initiates a HIGH-to-LO transition of. The rising edge of causes the data outputs to go to the high impedance state and remain such until a write is performed. eads to an empty FIFO are ignored and do not increment the read pointer. From the empty condition, the FIFO can be read t after a valid write. The retransmit feature is beneficial when transferring packets of data. It enables the receiver to acknowledge receipt of data and retransmit, if necessary. The etransmit (T) input is active in the standalone and width expansion modes. The retransmit feature is intended for use when a number of writes equal to or less than the depth of the FIFO have occurred since the last M cycle. A LO pulse on T resets the internal read pointer to the first physical location of the FIFO. and must both be HIGH while and t T after retransmit is LO. ith every read cycle after retransmit, previously accessed data and not previously accessed data is read and the read pointer is incremented until it is equal to the write pointer. Full, Half Full, and Empty flags are governed by the relative locations of the read and write pointers and are updated during a retransmit cycle. Data written to the FIFO after activation of T are also transmitted. FIFO, up to the full depth, can be repeatedly retransmitted. Standalone/idth Expansion Modes Standalone and width expansion modes are set by grounding Expansion In (XI) and tying First Load (FL) to V CC. FIFOs can be expanded in width to provide word widths greater than nine in increments of nine. During width expansion mode, all control line inputs are common to all devices, and flag outputs from any device can be monitored. Depth Expansion Mode Depth expansion mode (see Figure on page 12) is entered when, during a M cycle, Expansion Out (XO) of one device is connected to Expansion In (XI) of the next device, with XO of the last device connected to XI of the first device. In the depth expansion mode the First Load (FL) input, when grounded, indicates that this part is the first to be loaded. All other devices must have this pin HIGH. To enable the correct FIFO, XO is pulsed LO when the last physical location of the previous FIFO is written to and pulsed LO again when the last physical location is read. Only one FIFO is enabled for read and one for write at any particular time. All other devices are in standby. FIFOs can also be expanded simultaneously in depth and width. Consequently, any depth or width FIFO can be created of word widths in increments of 9. hen expanding in depth, a composite must be created by Oing the s together. Likewise, a composite is created by Oing the s together. HF and T functions are not available in depth expansion mode. Document #: ev. *D Page 11 of 16

12 Use of the Empty and Full Flags To achieve maximum frequency, the flags must be valid at the beginning of the next cycle. However, because they can be updated by either edge of the read or write signal, they must be valid by one-half of a cycle. Cypress FIFOs meet this requirement; some competitors FIFOs do not. The reason for why the flags should be valid by the next cycle is complex. The effective pulse width violation phenomenon can occur at the full and empty boundary conditions, if the flags are not properly used. The empty flag must be used to prevent reading from an empty FIFO and the full flag must be used to prevent writing into a full FIFO. For example, consider an empty FIFO that is receiving read pulses. Because the FIFO is empty, the read pulses are ignored by the FIFO, and nothing happens. Next, a single word is written into the FIFO, with a signal that is asynchronous to the read signal. The (internal) state machine in the FIFO goes from empty to empty+1. However, it does this asynchronously with respect to the read signal, so that the effective pulse width of the read signal cannot be determined, because the state machine does not look at the read signal until it goes to the empty+1 state. Similarly, the minimum write pulse width may be violated by trying to write into a full FIFO, and asynchronously performing a read. The empty and full flags are used to avoid these effective pulse width violations, but to do this and operate at the maximum frequency, the flag must be valid at the beginning of the next cycle. Figure 13. Depth Expansion XO D 9 9 CY7C419 CY7C420/1 CY7C424/5 CY7C428/9 CY7C432/3 FL 9 Q V CC XI XO FULL 9 CY7C419 CY7C420/1 CY7C424/5 CY7C428/9 CY7C432/3 FL EMPTY XI XO * M 9 CY7C419 CY7C420/1 CY7C424/5 CY7C428/9 CY7C432/3 FL XI * FISTDEVICE Document #: ev. *D Page 12 of 16

13 Ordering Information Speed (ns) Ordering Code Package Diagram Package Type Operating ange 10 CY7C421 10AC Pin Thin Plastic Quad Flatpack Commercial CY7C421 10JC Pin Plastic Leaded Chip Carrier CY7C421 10JXC Pin Plastic Leaded Chip Carriers (Pb-free) CY7C421 10PC Pin (300-Mil) Molded DIP CY7C421 10VC Pin (300-Mil) Molded SOJ 15 CY7C421 15AC Pin Thin Plastic Quad Flatpack Commercial CY7C421 15AXC Pin Thin Plastic Quad Flatpack (Pb-free) CY7C421 15JC Pin Plastic Leaded Chip Carrier CY7C421 15JI Pin Plastic Leaded Chip Carrier Industrial CY7C421 15VI Pin (300-Mil) Molded SOJ 20 CY7C421 20JC Pin Plastic Leaded Chip Carrier Commercial CY7C421 20JXC Pin Plastic Leaded Chip Carriers (Pb-free) CY7C421 20PC Pin (300-Mil) Molded DIP CY7C421 20VC Pin (300-Mil) Molded SOJ CY7C421 20VXC Pin (300-Mil) Molded SOJ (Pb-free) CY7C421 20JI Pin Plastic Leaded Chip Carrier Industrial CY7C421 20JXI Pin Plastic Leaded Chip Carrier (Pb-free) 25 CY7C421 25JC Pin Plastic Leaded Chip Carrier Commercial CY7C421 25PC Pin (300-Mil) Molded DIP CY7C421 25VC Pin (300-Mil) Molded SOJ CY7C421 25JI Pin Plastic Leaded Chip Carrier Industrial CY7C421 25PI Pin (300-Mil) Molded DIP 30 CY7C421 30JC Pin Plastic Leaded Chip Carrier Commercial CY7C421 30PC Pin (300-Mil) Molded DIP CY7C421 30JI Pin Plastic Leaded Chip Carrier Industrial 40 CY7C421 40JC Pin Plastic Leaded Chip Carrier Commercial CY7C421 40PC Pin (300-Mil) Molded DIP CY7C421 40VC Pin (300-Mil) Molded SOJ CY7C421 40JI Pin Plastic Leaded Chip Carrier Industrial 65 CY7C421 65JC Pin Plastic Leaded Chip Carrier Commercial CY7C421 65PC Pin (300-Mil) Molded DIP CY7C421 65VC Pin (300-Mil) Molded SOJ CY7C421 65JI Pin Plastic Leaded Chip Carrier Industrial Document #: ev. *D Page 13 of 16

14 Package Diagrams Figure Pin Thin Plastic Quad Flat Pack, *B Figure Pin Plastic Leaded Chip Carrier, *B Document #: ev. *D Page 14 of 16

15 Package Diagrams Figure Pin (300-Mil) PDIP, SEE LEAD END OPTION [6.60] 0.295[7.49] DIMENSIONS IN INCHES [MM] MIN. MAX. EENCE JEDEC MO-095 PACKAGE EIGHT: 2.15 gms [0.76] 0.080[2.03] SEATING PLANE 1.345[34.16] 1.385[35.18] 0.290[7.36] 0.325[8.25] 0.140[3.55] 0.190[4.82] 0.120[3.05] 0.140[3.55] 0.115[2.92] 0.160[4.06] 0.090[2.28] 0.110[2.79] 0.055[1.39] 0.065[1.65] 0.015[0.38] 0.020[0.50] 0.015[0.38] 0.060[1.52] SEE LEAD END OPTION 0.009[0.23] 0.012[0.30] 0.310[7.87] 0.385[9.78] 3 MIN. LEAD END OPTION (LEAD #1, 14, 15 & 28) *D Figure Pin (300-Mil) Molded SOJ, DIMENSIONS IN INCHES MIN. MAX. PIN 1 ID A DETAIL EXTENAL LEAD DESIGN OPTION 1 OPTION SEATING PLANE TYP. A MIN *B Document #: ev. *D Page 15 of 16

16 Document History Page Document Title: CY7C419/21/25/29/33, 256/512/1K/2K/4Kx9 Asynchronous FIFO Document Number: ev. ECN No. Orig. of Change Sales, Solutions, and Legal Information orldwide Sales and Design Support Submission Date Description of Change ** SZV 07/11/01 Change from Spec Number: to *A BI 12/30/02 Added power up requirements to maximum ratings information. *B PCX See ECN Added Pb-Free Logo Added to Part-Ordering Information: CY7C419 10JXC, CY7C419 15JXC, CY7C419-15VXC, CY7C421 10JXC, CY7C421 15AXC, CY7C421 20JXC, CY7C421 20VXC, CY7C425 10AXC, CY7C425 10JXC, CY7C425 15JXC, CY7C425 20JXC, CY7C425 20VXC, CY7C429 10AXC, CY7C429 15JXC, CY7C429 20JXC, CY7C433 10AXC, CY7C433 10JXC, CY7C433 15JXC, CY7C433 20AXC, CY7C433 20JXC *C VKN/PYS 12/17/08 Added CY7C421-20JXI emoved CY7C419/25/29/33 from the ordering information table emoved 26-Lead CerDIP, 32-Lead LCC, 28-Lead molded DIP packages from the data sheet emoved Military Information *D VKN/AESA 06/04/2009 Corrected defective Logic Block diagram, Pinouts, and Package diagrams Cypress maintains a worldwide network of offices, solution centers, manufacturer s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales. Products PSoC Clocks & Buffers ireless Memories Image Sensors psoc.cypress.com clocks.cypress.com wireless.cypress.com memory.cypress.com image.cypress.com Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPESS MAKES NO AANTY OF ANY KIND, EXPESS O IMPLIED, ITH EGAD TO THIS MATEIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED AANTIES OF MECHANTABILITY AND FITNESS FO A PATICULA PUPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document #: ev. *D evised June 03, 2009 Page 16 of 16 All products and company names mentioned in this document may be the trademarks of their respective holders.