CMOS ASYNCHRONOUS FIFO 2048 x 9, 4096 x 9, 8192 x 9 and x 9

Transcription

1 Integrated Device Technology, Inc. CMOS ASYNCHONOUS FIFO 2048 x, 406 x, 812 x and x FEATUES: First-In/First-Out Dual-Port memory 2048 x organization (7203) 406 x organization (7204) 812 x organization (7205) x organization () High-speed: 12ns access time Low power consumption Active: 770m (max.) Power-down: 44m (max.) Asynchronous and simultaneous read and write Fully expandable in both word depth and width Pin and functionally compatible with 720X family Status Flags: Empty, Half-Full, Full etransmit capability High-performance CMOS technology Military product compliant to MIL-STD-883, Class B Standard Military Drawing for # (7203), (7203), and (7204) are listed on this function Industrial temperature range (-40 o C to +85 o C) is available, tested to military electrical specifications. DESCIPTION: The 7204/ are dual-port memory buffers with internal pointers that load and empty data on a firstin/first-out basis. The device uses Full and Empty flags to prevent data overflow and underflow and expansion logic to allow for unlimited expansion capability in both word size and depth. Data is toggled in and out of the device through the use of the rite () and ead () pins. The devices -bit width provides a bit for a control or parity at the user s option. It also features a etransmit (T) capability that allows the read pointer to be reset to its initial position when T is pulsed LO. A Half-Full Flag is available in the single device and width expansion modes. The 7204/ are fabricated using s high-speed CMOS technology. They are designed for applications requiring asynchronous and simultaneous read/writes in multiprocessing, rate buffering, and other applications. Military grade product is manufactured in compliance with the latest revision of MIL-STD-883, Class B. FUNCTIONAL BLOCK DIAGAM ITE CONTOL DATA INPUTS (D 0 D8) ITE POINTE AM AAY 2048 x 406 x 812 x x EAD POINTE EAD CONTOL THEE- STATE BUES DATA OUTPUTS (Q 0 Q8) S ESET LOGIC FLAG LOGIC FL/T EXPANSION LOGIC XO/HF 2661 drw 01 The logo is a registered trademark of Integrated Device Techology, Inc. MILITAY AND COMMECIAL TEMPEATUE ANGES DECEMBE Integrated Device Technology, Inc. For latest information contact 's web site at or fax-on-demand at DSC-2661/

2 7204/ CMOS ASYNCHONOUS FIFO 2048 x, 406 x, 812 x and x MILITAY AND COMMECIAL TEMPEATUE ANGES PIN CONFIGUATIONS D 8 D3 D2 D1 D0 Q0 Q1 Q2 Q 3 Q8 GND P28-1 P28-2 D28-1 D28-3 SO28-3 Vcc D4 26 D5 25 D6 24 D S DIP TOP VIE FL/T XO/HF Q7 Q6 Q5 Q drw 02a INDEX D2 D1 D0 Q0 Q1 NC Q D3 D8 NC Vcc J32-1 & L Q3 Q8 1 GND NC PLCC/LCC TOP VIE D 4 D Q4 Q D 6 D 7 NC FL/T S XO/HF Q 7 Q drw 02b NOTES: 1. The THINDIPs P28-2 and D28-3 are only available for the 7204/ The small outline package SO28-3 is only available for the Consult factory for CEPACK pinout. ABSOLUTE MAMUM ATINGS (1) Symbol ating Commercial Military Unit VTEM Terminal 0.5 to to +7.0 V Voltage with espect to GND TA Operating 0 to to +125 C Temperature TBIAS Temperature 55 to to +135 C Under Bias TSTG Storage 55 to to +155 C Temperature IOUT DC Output ma Current NOTE: 2661 tbl Stresses greater than those listed under ABSOLUTE MAMUM AT- INGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. ECOMMENDED DC OPEATING CONDITIONS Symbol Parameter Min. Typ. Max. Unit VCCM Military Supply V Voltage VCCC Commercial Supply V Voltage GND Supply Voltage V VIH (1) Input High Voltage 2.0 V Commercial VIH (1) Input High Voltage 2.2 V Military VIL (1) Input Low Voltage 0.8 V Commercial and Military NOTE: 2661 tbl V undershoots are allowed for 10ns once per cycle

3 7204/ CMOS ASYNCHONOUS FIFO 2048 x, 406 x, 812 x and x MILITAY AND COMMECIAL TEMPEATUE ANGES DC ELECTICAL CHAACTEISTICS FO THE 7203 AND 7204 (Commercial: VCC = 5.0V±10%, TA = 0 C to +70 C; Military: VCC = 5.0V±10%, TA = 55 C to +125 C) Commercial Military (1) ta = 12, 15, 20, 25, 35, 50 ns ta = 20, 30, 40, 50, 65, 80, 120 ns Symbol Parameter Min. Typ. Max. Min. Typ. Max. Unit ILI (2) Input Leakage Current (Any Input) µa ILO (3) Output Leakage Current µa VOH Output Logic 1 Voltage IOH = 2mA V VOL Output Logic 0 Voltage IOL = 8mA V ICC1 (4) Active Power Supply Current 120 (5) 150 (5) ma ICC2 (4) Standby Current (==S=FL/T=VIH) ma ICC3(L) (4) Power Down Current (All Input = VCC - 0.2V) 2 4 ma ICC3(S) (4) Power Down Current (All Input = VCC - 0.2V) 8 12 ma NOTES: 2661 tbl Speed grades 65, 80, and 120ns are only available in the ceramic DIP. 2. Measurements with 0.4 VIN VCC. 3. VIH, 0.4 VOUT VCC. 4. ICC measurements are made with outputs open (only capacitive loading). 5. Tested at f = 20MHz. DC ELECTICAL CHAACTEISTICS FO THE 7205 AND (Commercial: VCC = 5.0V±10%, TA = 0 C to +70 C; Military: VCC = 5.0V±10%, TA = 55 C to +125 C) Commercial Military ta = 15, 20, 25, 35, 50 ns ta = 20, 30, 50 ns Symbol Parameter Min. Typ. Max. Min. Typ. Max. Unit ILI (1) Input Leakage Current (Any Input) µa ILO (2) Output Leakage Current µa VOH Output Logic 1 Voltage IOH = 2mA V VOL Output Logic 0 Voltage IOL = 8mA V ICC1 (3) Active Power Supply Current 120 (4) 150 (4) ma ICC2 (3) Standby Current (==S=FL/T=VIH) ma ICC3(L) (3) Power Down Current (All Input = VCC - 0.2V) 8 12 ma NOTES: 2661 tbl Measurements with 0.4 VIN VCC. 2. VIH, 0.4 VOUT VCC. 3. ICC measurements are made with outputs open (only capacitive loading). 4. Tested at f = 20MHz

4 7204/ CMOS ASYNCHONOUS FIFO 2048 x, 406 x, 812 x and x MILITAY AND COMMECIAL TEMPEATUE ANGES AC ELECTICAL CHAACTEISTICS (1) (Commercial: VCC = 5V ± 10%, TA = 0 C to +70 C; Military: VCC = 5V ± 10%, TA = 55 C to +125 C) Commercial Com'l & Mil. Com'l Military Com'l 7203S/L S/L S/L S/L S/L S/L S/L S/L S/L S/L S/L S/L L L L L L35 L15 L20 L25 L30 L35 Symbol Parameters Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit fs Shift Frequency MHz tc ead Cycle Time ns ta Access Time ns t ead ecovery Time ns tp ead Pulse idth (2) ns tlz ead LO to Data Bus LO (3) ns tlz rite HIGH to Data Bus Low-Z (3, 4) ns tdv Data Valid from ead HIGH ns thz ead HIGH to Data Bus High-Z (3) ns tc rite Cycle Time ns tp rite Pulse idth (2) ns t rite ecovery Time ns tds Data Set-up Time ns tdh Data Hold Time ns tsc eset Cycle Time ns ts eset Pulse idth (2) ns tss eset Set-up Time (3) ns tt eset ecovery Time ns ttc etransmit Cycle Time ns tt etransmit Pulse idth (2) ns tts etransmit Set-up Time (3) ns ts etransmit ecovery Time ns tl eset to LO ns thfh, th eset to HF and HIGH ns ttf etransmit LO to Flags Valid ns t ead LO to LO ns t ead HIGH to HIGH ns tpe ead Pulse idth after HIGH ns t rite HIGH to HIGH ns t rite LO to LO ns thf rite LO to HF Flag LO ns thf ead HIGH to HF Flag HIGH ns tpf rite Pulse idth after HIGH ns txol ead/rite LO to XO LO ns txoh ead/rite HIGH to XO HIGH ns t Pulse idth (2) ns t ecovery Time ns ts Set-up Time ns NOTES: 2661 tbl Timings referenced as in AC Test Conditions. 2. Pulse widths less than minimum are not allowed. 3. Values guaranteed by design, not currently tested. 4. Only applies to read data flow-through mode

5 7204/ CMOS ASYNCHONOUS FIFO 2048 x, 406 x, 812 x and x MILITAY AND COMMECIAL TEMPEATUE ANGES AC ELECTICAL CHAACTEISTICS (1) (Continued) (Commercial: VCC = 5V ± 10%, TA = 0 C to +70 C; Military: VCC = 5V ± 10%, TA = 55 C to +125 C) Military Com'l & Mil. Military (2) 7203S/L S/L S/L S/L S/L S/L S/L S/L S/L S/L L50 L50 Symbol Parameters Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit fs Shift Frequency MHz tc ead Cycle Time ns ta Access Time ns t ead ecovery Time ns tp ead Pulse idth (3) ns tlz ead LO to Data Bus LO (4) ns tlz rite HIGH to Data Bus Low-Z (4, 5) ns tdv Data Valid from ead HIGH ns thz ead HIGH to Data Bus High-Z (4) ns tc rite Cycle Time ns tp rite Pulse idth (3) ns t rite ecovery Time ns tds Data Set-up Time ns tdh Data Hold Time ns tsc eset Cycle Time ns ts eset Pulse idth (3) ns tss eset Set-up Time (4) ns ts eset ecovery Time ns ttc etransmit Cycle Time ns tt etransmit Pulse idth (3) ns tts etransmit Set-up Time (4) ns ts etransmit ecovery Time ns tl eset to LO ns thfh, th eset to HF and HIGH ns ttf etransmit LO to Flags Valid ns t ead LO to Flag LO ns t ead HIGH to HIGH ns tpe ead Pulse idth after HIGH ns t rite HIGH to HIGH ns t rite LO to LO ns thf rite LO to HF LO ns thf ead HIGH to HF HIGH ns tpf rite Pulse idth after HIGH ns txol ead/rite LO to XO LO ns txoh ead/rite HIGH to XO HIGH ns t Pulse idth (3) ns t ecovery Time ns ts Set-up Time ns NOTES: 2661 tbl Timings referenced as in AC Test Conditions. 2. Speed grades 65, 80, and 120ns are only available in the ceramic DIP. 3. Pulse widths less than minimum are not allowed. 4. Values guaranteed by design, not currently tested. 5. Only applies to read data flow-through mode

6 7204/ CMOS ASYNCHONOUS FIFO 2048 x, 406 x, 812 x and x MILITAY AND COMMECIAL TEMPEATUE ANGES AC TEST CONDITIONS 5V Input Pulse Levels Input ise/fall Times Input Timing eference Levels Output eference Levels Output Load GND to 3.0V 5ns 1.5V 1.5V See Figure tbl 07 D.U.T. 680Ω 1.1KΩ 30pF* CAPACITANCE (1) (TA = +25 C, f = 1.0 MHz) Symbol Parameter Condition Max. Unit CIN (1) Input Capacitance VIN = 0V 10 pf COUT (1,2) Output Capacitance VOUT = 0V 10 pf NOTES: 2661 tbl This parameter is sampled and not 100% tested. 2. ith output deselected drw 03 O EQUIVALENT CICUIT Figure 1. Output Load *Includes jig and scope capacitances. SIGNAL DESCIPTIONS Inputs: DATA IN (D0 D8) Data inputs for -bit wide data. Controls: ESET (S) eset is accomplished whenever the eset (S) input is taken to a LO state. During reset, both internal read and write pointers are set to the first location. A reset is required after power-up before a write operation can take place. Both the ead Enable () and rite Enable () inputs must be in the HIGH state during the window shown in Figure 2 (i.e. tss before the rising edge of S) and should not change until ts after the rising edge of S. ITE ENABLE () A write cycle is initiated on the falling edge of this input if the Full Flag () is not set. Data set-up and hold times must be adhered-to, with respect to the rising edge of the rite Enable (). Data is stored in the AM array sequentially and independently of any on-going read operation. After half of the memory is filled, and at the falling edge of the next write operation, the Half-Full Flag (HF) will be set to LO, and will remain set until the difference between the write pointer and read pointer is less-than or equal to one-half of the total memory of the device. The Half-Full Flag (HF) is reset by the rising edge of the read operation. To prevent data overflow, the Full Flag () will go LO on the falling edge of the last write signal, which inhibits further write operations. Upon the completion of a valid read operation, the Full Flag () will go HIGH after t, allowing a new valid write to begin. hen the FIFO is full, the internal write pointer is blocked from, so external changes in will not affect the FIFO when it is full. EAD ENABLE () A read cycle is initiated on the falling edge of the ead Enable (), provided the Empty Flag () is not set. The data is accessed on a First-In/First-Out basis, independent of any ongoing write operations. After ead Enable () goes HIGH, the Data Outputs (Q0 through Q8) will return to a high-impedance condition until the next ead operation. hen all the data has been read from the FIFO, the Empty Flag () will go LO, allowing the final read cycle but inhibiting further read operations, with the data outputs remaining in a highimpedance state. Once a valid write operation has been accomplished, the Empty Flag () will go HIGH after t and a valid ead can then begin. hen the FIFO is empty, the internal read pointer is blocked from so external changes will not affect the FIFO when it is empty. FIST LOAD/ETANSMIT (FL/T) This is a dualpurpose input. In the Depth Expansion Mode, this pin is grounded to indicate that it is the first device loaded (see Operating Modes). The Single Device Mode is initiated by grounding the Expansion In (). The 7204/ can be made to retransmit data when the etransmit Enable Control (T) input is pulsed LO. A retransmit operation will set the internal read pointer to the first location and will not affect the write pointer. The status of the Flags will change depending on the relative locations of the read and write pointers. ead Enable () and rite Enable () must be in the HIGH state during retransmit. This feature is useful when less than 2048/406/812/16384 writes are performed between resets. The retransmit feature is not compatible with the Depth Expansion Mode. EXPANSION IN () This input is a dual-purpose pin. Expansion In () is grounded to indicate an operation in the single device mode. Expansion In () is connected to Expansion Out (XO) of the previous device in the Depth Expansion or Daisy-Chain Mode

7 7204/ CMOS ASYNCHONOUS FIFO 2048 x, 406 x, 812 x and x MILITAY AND COMMECIAL TEMPEATUE ANGES Outputs: FULL FLAG () The Full Flag () will go LO, inhibiting further write operations, when the device is full. If the read pointer is not moved after eset (S), the Full Flag () will go LO after 2048/406/812/16384 writes. EMPTY FLAG () The Empty Flag () will go LO, inhibiting further read operations, when the read pointer is equal to the write pointer, indicating that the device is empty. EXPANSION OUT/HALF-FULL FLAG (XO/HF) This is a dual-purpose output. In the single device mode, when Expansion In () is grounded, this output acts as an indication of a halffull memory. After half of the memory is filled, and at the falling edge of the next write operation, the Half-Full Flag (HF) will be set to LO and will remain set until the difference between the write pointer and read pointer is less than or equal to one half of the total memory of the device. The Half-Full Flag (HF) is then reset by the rising edge of the read operation. In the Depth Expansion Mode, Expansion In () is connected to Expansion Out (XO) of the previous device. This output acts as a signal to the next device in the Daisy Chain by providing a pulse to the next device when the previous device reaches the last location of memory. There will be an XO pulse when the rite pointer reaches the last location of memory, and an additional XO pulse when the ead pointer reaches the last location of memory. DATA OUTPUTS (Q0-Q8) Q0-Q8 are data outputs for - bit wide data. These outputs are in a high-impedance condition whenever ead () is in a HIGH state. S t S tsc t SS t S t SS t L t HFH, t H HF, NOTE: 1. and = VIH around the rising edge of S. Figure 2. eset 2661 drw 04 t A t C t ta t P Q0 Q8 t LZ t DV DATAOUT VALID t HZ DATAOUT VALID t C t P t t DS t DH D0 D8 DATA IN VALID DATA IN VALID 2661 drw 05 Figure 3. Asynchronous rite and ead Operation

8 7204/ CMOS ASYNCHONOUS FIFO 2048 x, 406 x, 812 x and x MILITAY AND COMMECIAL TEMPEATUE ANGES LAST ITE IGNOED ITE FIST EAD t t 2661 drw 06 Figure 4. Full FlagTiming From Last rite to First ead LAST EAD IGNOED EAD FIST ITE DATA OUT t t A VALID t 2661 drw 07 Figure 5. Empty Flag Timing From Last ead to First rite t TC t T T, t TS TF t T HF,, FLAG VALID 2661 drw 08 NOTE: 1., and HF may change status during etransmit, but flags will be valid at ttc. Figure 6. etransmit

9 7204/ CMOS ASYNCHONOUS FIFO 2048 x, 406 x, 812 x and x MILITAY AND COMMECIAL TEMPEATUE ANGES t t PE 2661 drw 0 Figure 7. Minimum Timing for an Empty Flag Coincident ead Pulse. t t PF 2661 drw 10 Figure 8. Minimum Timing for an Full Flag Coincident rite Pulse. t HF t HF HF HALF-FULL O LESS MOE THAN HALF-FULL HALF-FULL O LESS Figure. Half-Full Flag Timing 2661 drw 11 ITE TO LAST PHYSICAL LOCATION t XOL t XOH EAD FOM LAST PHYSICAL LOCATION t XOL t XOH XO 2661 drw 12 Figure 10. Expansion Out 5.04

10 7204/ CMOS ASYNCHONOUS FIFO 2048 x, 406 x, 812 x and x MILITAY AND COMMECIAL TEMPEATUE ANGES t t t S ITE TO FIST PHYSICAL LOCATION t S EAD FOM FIST PHYSICAL LOCATION Figure 11. Expansion In 2661 drw 11 OPEATING MODES: Care must be taken to assure that the appropriate flag is monitored by each system (i.e. is monitored on the device where is used; is monitored on the device where is used). For additional information, refer to Tech Note 8: Operating FIFOs on Full and Empty Boundary Conditions and Tech Note 6: Designing with FIFOs. Single Device Mode A single 7204/ may be used when the application requirements are for 2048/406/812/16384 words or less. The 7204/ is in a Single Device Configuration when the Expansion In () control input is grounded (see Figure 12). Depth Expansion The 7204/ can easily be adapted to applications when the requirements are for greater than 2048/ 406/812/16384 words. Figure 14 demonstrates Depth Expansion using three 7204/s. Any depth can be attained by adding additional 7204/ s. The 7204/ operates in the Depth Expansion mode when the following conditions are met: 1. The first device must be designated by grounding the First Load (FL) control input. 2. All other devices must have FL in the HIGH state. 3. The Expansion Out (XO) pin of each device must be tied to the Expansion In () pin of the next device. See Figure External logic is needed to generate a composite Full Flag () and Empty Flag (). This requires the Oing of all s and Oing of all s (i.e. all must be set to generate the correct composite or ). See Figure The etransmit (T) function and Half-Full Flag (HF) are not available in the Depth Expansion Mode. For additional information, refer to Tech Note : Cascading FIFOs or FIFO Modules. USAGE MODES: idth Expansion ord width may be increased simply by connecting the corresponding input control signals of multiple devices. Status flags (, and HF) can be detected from any one device. Figure 13 demonstrates an 18-bit word width by using two 7204/s. Any word width can be attained by adding additional 7204/s (Figure 13). Bidirectional Operation Applications which require data buffering between two systems (each system capable of ead and rite operations) can be achieved by pairing 7204/s as shown in Figure 16. Both Depth Expansion and idth Expansion may be used in this mode. Data Flow-Through Two types of flow-through modes are permitted, a read flow-through and write flow-through mode. For the read flowthrough mode (Figure 17), the FIFO permits a reading of a single word after writing one word of data into an empty FIFO. The data is enabled on the bus in (t + ta) ns after the rising edge of, called the first write edge, and it remains on the bus until the line is raised from LO-to-HIGH, after which the bus would go into a three-state mode after thz ns. The line would have a pulse showing temporary deassertion and then would be asserted. In the write flow-through mode (Figure 18), the FIFO permits the writing of a single word of data immediately after reading one word of data from a full FIFO. The line causes the to be deasserted but the line being LO causes it to be asserted again in anticipation of a new data word. On the rising edge of, the new word is loaded in the FIFO. The line must be toggled when is not asserted to write new data in the FIFO and to increment the write pointer. Compound Expansion The two expansion techniques described above can be applied together in a straightforward manner to achieve large FIFO arrays (see Figure 15)

11 7204/ CMOS ASYNCHONOUS FIFO 2048 x, 406 x, 812 x and x MILITAY AND COMMECIAL TEMPEATUE ANGES (HALF FULL FLAG) (HF) ITE () DATA IN (D) FULL FLAG () ESET (S) 7204/ EAD () DATA OUT (Q) EMPTY FLAG () ETANSMIT (T) EXPANSION IN () 2661 drw 14 Figure 12. Block Diagram of 2048 x /406 x /812 x /16384 x FIFO Used in Single Device Mode HF HF 18 DATA IN (D) ITE () FULL FLAG () ESET (S) 7204/ 7204/ EAD () EMPTY FLAG () ETANSMIT (T) 18 DATA OUT(Q) 2661 drw 15 NOTE: 1. Flag detection is accomplished by monitoring the, and HF signals on either (any) device used in the width expansion configuration. Do not connect any output signals together. Figure 13. Block Diagram of 2048 x 18/406 x 18/812 x 18/16384 x 18 FIFO Memory Used in idth Expansion Mode

12 7204/ CMOS ASYNCHONOUS FIFO 2048 x, 406 x, 812 x and x MILITAY AND COMMECIAL TEMPEATUE ANGES TUTH TABLES TABLE I ESET AND ETANSMIT SINGLE DEVICE CONFIGUATION/H EXPANSION MODE Mode S Inputs Internal Status Outputs T ead Pointer rite Pointer eset 0 X 0 Location Zero Location Zero etransmit Location Zero Unchanged X X X ead/rite Increment (1) Increment (1) X X X NOTE: 2661 tbl 0 1. Pointer will Increment if flag is HIGH. HF TABLE II ESET AND FIST LOAD DEPTH EXPANSION/COMPOUND EXPANSION MODE Mode S Inputs Internal Status Outputs FL ead Pointer rite Pointer eset First Device 0 0 (1) Location Zero Location Zero 0 1 eset all Other Devices 0 1 (1) Location Zero Location Zero 0 1 ead/rite 1 X (1) X X X X NOTES: 2661 tbl is connected to XO of previous device. See Figure S = eset Input, FL/T = First Load/etransmit, = Empty Flag Output, = Full Flag Output, = Expansion Input, HF = Half-Full Flag Output D XO 7204/ Q FL VCC XO FULL 7204/ FL EMPTY XO S 7204/ FL 2661 drw 16 Figure 14. Block Diagram of 614 x /1228 x /2456 x /4152 x FIFO Memory (Depth Expansion)

13 7204/ CMOS ASYNCHONOUS FIFO 2048 x, 406 x, 812 x and x MILITAY AND COMMECIAL TEMPEATUE ANGES Q 0 Q 8 Q Q 17 Q0 Q 8 Q Q 17 Q (N-8) -Q N Q (N-8) -Q N 7204/ 7204/,, S DEPTH DEPTH EXPANSION BLOCK EXPANSION BLOCK 7204/ DEPTH EXPANSION BLOCK D0 D N D 0 -D 8 D -D 17 D (N-8)-D N D -D N NOTES: 1. For depth expansion block see section on Depth Expansion and Figure For Flag detection see section on idth Expansion and Figure 13. D 18 -D N D (N-8)-D N 2661 drw 17 Figure 15. Compound FIFO Expansion A A DA / 7201A QB 0-8 B B HF B SYSTEM A SYSTEM B QA 0-8 A HFA A 7204/ DB 0-8 B B 2661 drw 18 Figure 16. Bidirectional FIFO Operation DATA IN t PE t LZ t t A t DATA OUT DATA VALIDOUT Figure 17. ead Data Flow-Through Mode 2661 drw

14 7204/ CMOS ASYNCHONOUS FIFO 2048 x, 406 x, 812 x and x MILITAY AND COMMECIAL TEMPEATUE ANGES t PF t t t DH DATA IN DATA IN VALID t A t DS DATA OUT DATA OUT VALID Figure 18. rite Data Flow-Through Mode 2661 drw 20 ODEING INFOMATION XXXX X XX X X DeviceType Power Speed Package Process/ Temperature ange Blank B Commercial (0 C to +70 C) Military ( 55 C to +125 C) Compliant to MIL-STD-883, Class B P TP D TD J L SO Plastic DIP Plastic THINDIP Ceramic DIP Ceramic THINDIP (all except ) Plastic Leaded Chip Carrier Leadless Chip Carrier (Military only) Small Outline IC (7204 only) Commercial 04 Only Commercial Only Commercial Only Military Only Commercial Only Military 04 Only Military 04DB Only Access Time (ta) Speed in ns S L Standard Power (7204 only) Low Power 2048 x FIFO 406 x FIFO 812 x FIFO x FIFO 2661 drw

15 This datasheet has been downloaded from: Datasheets for electronic components.