3.3 VOLT CMOS ASYNCHRONOUS FIFO 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9, 8,192 x 9, 16,384 x 9 WRITE POINTER THREE- STATE BUFFERS DATA OUTPUTS FLAG

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1 3.3 VOLT CMOS ASYNCHONOUS FIFO 512 x, 1,024 x, 2,048 x, 4,06 x, 8,12 x, 16,384 x LEAD FINISH (SnPb) AE IN EOL POCESS - LAST TIME BUY EXPIES JUNE 15, 2018 FEATUES: 3.3V family uses less power than the 5 Volt 7201/7202/7203/7204/ 7205/7206 family 512 x organization () 1,024 x organization () 2,048 x organization () 4,06 X organization () 8,12 x organization () 16,384 X organization () Functionally compatible with 720x family Low-power consumption Active: 180 m (max.) Power-down: 18 m (max.) 15 ns access time Asynchronous and simultaneous read and write Fully expandable by both word depth and/or bit width Status Flags: Empty, Half-Full, Full Auto-retransmit capability Available in 32-pin PLCC Industrial temperature range ( 40 C to +85 C) is available Green parts available, see ordering information,,, DESCIPTION: The ///// are dual-port FIFO memories that operate at a power supply voltage (Vcc) between 3.0V and 3.6V. Their architecture, functional operation and pin assignments are identical to those of the 7201/7202/7203/7204/7205/7206. These devices load and empty data on a first-in/first-out basis. They use Full and Empty flags to prevent data overflow and underflow and expansion logic to allow for unlimited expansion capability in both word size and depth. The reads and writes are internally sequential through the use of ring pointers, with no address information required to load and unload data. Data is toggled in and out of the devices through the use of the rite () and ead () pins. The devices have a maximum data access time as fast as 25 ns. The devices utilize a -bit wide data array to allow for control and parity bits at the user s option. This feature is especially useful in data communications applications where it is necessary to use a parity bit for transmission/reception error checking. They also feature a etransmit (T) capability that allows for reset of the read pointer to its initial position when T is pulsed LO to allow for retransmission from the beginning of data. A Half-Full Flag is available in the single device mode and width expansion modes. These FIFOs are fabricated using high-speed CMOS technology. It has been designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications. FUNCTIONAL BLOCK DIAGAM ITE CONTOL DATA INPUTS (D0-D8) ITE POINTE AM AAY 512 x 1,024 x 2,048 x 4,06 x 8,12 x 16,384 x EAD POINTE EAD CONTOL THEE- STATE BUES DATA OUTPUTS (Q0-Q8) S ESET LOGIC FLAG LOGIC FL/T EXPANSION LOGIC XO/HF 3033 drw 01 and the logo are trademarks of Integrated Device Technology, Inc COMMECIAL AND INDUSTIAL TEMPEATUE ANGES 1 NOVEMBE Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. DSC-3033/8

2 ///// 3.3V ASYNCHONOUS FIFO COMMECIAL AND INDUSTIAL TEMPEATUE ANGES PIN CONFIGUATION INDEX D2 5 D1 6 D0 7 8 Q0 10 Q1 11 NC 12 Q2 13 D3 D Q3 NC Q8 GND NC VCC D4 D5 Q4 Q D6 D7 NC FL/T S XO/HF Q7 Q drw 02b ABSOLUTE MAMUM ATINGS Symbol ating Com'l & Ind'l Unit VTEM Terminal Voltage 0.5 to +7.0 V with espect to GND TSTG Storage Temperature 55 to +125 C IOUT DC Output Current 50 to +50 ma NOTE: 1. Stresses greater than those listed under ABSOLUTE MAMUM ATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. ECOMMENDED DC OPEATING CONDITIONS Symbol ating Min. Typ. Max. Unit VCC Supply Voltage V GND Supply Voltage V VIH (1) Input High Voltage 2.0 VCC+0.5 V VIL (2) Input Low Voltage 0.8 V TA Operating Temperature Commercial 0 70 C TA Operating Temperature Industrial C PLCC (J32-1, order code: J) TOP VIE NOTES: 1. For T/S/ input, VIH = 2.6V (commercial). For T/S/ input, VIH = 2.8V (military) V undershoots are allowed for 10ns once per cycle. DC ELECTICAL CHAACTEISTICS (Commercial: VCC = 3.3V ± 0.3V, TA = 0 C to +70 C; Industrial: VCC = 3.3V ± 0.3V, TA = 40 C to +85 C) Commercial & Industrial (1) Commercial & Industrial (1) ta = 15, 25, 35 ns ta = 15, 25, 35 ns Symbol Parameter Min. Max. Min. Max. Unit ILI (2) Input Leakage Current (Any Input) µa ILO (3) Output Leakage Current µa VOH Output Logic 1 Voltage IOH = 2mA V VOL Output Logic 0 Voltage IOL = 8mA V ICC1 (4,5) Active Power Supply Current ma ICC2 (4,6) Standby Current (==S=FL/T=VIH) 5 5 ma NOTES: 1. Industrial temperature range product for the 25ns speed grade is available as a standard device. All other speed grades are available by special order. 2. Measurements with 0.4 VIN VCC. 3. VIH, 0.4 VOUT VCC. 4. Tested with outputs open (IOUT = 0). 5. Tested at f = 20 MHz. 6. All Inputs = VCC - 0.2V or GND + 0.2V. CAPACITANCE (TA = +25 C, f = 1.0 MHz) Symbol Parameter (1) Condition Max. Unit CIN Input Capacitance VIN = 0V 8 pf COUT Output Capacitance VOUT = 0V 8 pf NOTE: 1. Characterized values, not currently tested. 2

3 ///// 3.3V ASYNCHONOUS FIFO COMMECIAL AND INDUSTIAL TEMPEATUE ANGES AC ELECTICAL CHAACTEISTICS (1) (Commercial: VCC = 3.3V ± 0.3V, TA = 0 C to +70 C; Industrial: VCC = 3.3V ± 0.3V, TA = 40 C to +85 C) Commercial Com'l and Ind'l (2) Commercial L15 L25 L35 L15 L25 L35 L15 L25 L35 L15 L15 L25 L25 L35 L35 L15 L25 L35 Symbol Parameter Min. Max. Min. Max. Min. Max. Unit fs Shift Frequency MHz tc ead Cycle Time ns ta Access Time ns t ead ecovery Time ns tp ead Pulse idth (3) ns tlz ead Pulse Low to Data Bus at Low Z (4) ns tlz rite Pulse High to Data Bus at Low Z (4,5) ns tdv Data Valid from ead Pulse High ns thz ead Pulse High to Data Bus at High Z (4) ns tc rite Cycle Time ns tp rite Pulse idth (3) ns t rite ecovery Time ns tds Data Setup Time ns tdh Data Hold Time ns tsc eset Cycle Time ns ts eset Pulse idth (3) ns tss eset Setup Time (4) ns ts eset ecovery Time ns ttc etransmit Cycle Time ns tt etransmit Pulse idth (3) ns tts etransmit Setup Time (4) ns tt etransmit ecovery Time ns tl eset to Empty Flag Low ns thfh,h eset to Half-Full and Full Flag High ns ttf etransmit Low to Flags Valid ns t ead Low to Empty Flag Low ns t ead High to Full Flag High ns tpe ead Pulse idth after High ns t rite High to Empty Flag High ns t rite Low to Full Flag Low ns thf rite Low to Half-Full Flag Low ns thf ead High to Half-Full Flag High ns tpf rite Pulse idth after High ns txol ead/rite to XO Low ns txoh ead/rite to XO High ns t Pulse idth (3) ns t ecovery Time ns ts Setup Time ns NOTES: 1. Timings referenced as in AC Test Conditions. 2. Industrial temperature range product for the 25ns speed grade is available as a standard device. All other speed grades are available by special order. 3. Pulse widths less than minimum value are not allowed. 4. Values guaranteed by design, not currently tested. 5. Only applies to read data flow-through mode. AC TEST CONDITIONS Input Pulse Levels GND to 3.0V Input ise/fall Times 5ns Input Timing eference Levels 1.5V Output eference Levels 1.5V Output Load See Figure 1 3 D.U.T. 510Ω 3.3V or equivalent circuit 330Ω 30pF* Figure 1. Output Load * Includes scope and jig capacitances drw 03

4 ///// 3.3V ASYNCHONOUS FIFO COMMECIAL AND INDUSTIAL TEMPEATUE ANGES SIGNAL DESCIPTIONS INPUTS: DATA IN (D0 D8) Data inputs for -bit wide data. CONTOLS: ESET (S) eset is accomplished whenever the eset (S) input is taken to a LO state. During reset, both internal read and write pointers are set to the first location. A reset is required after power up before a write operation can take place. Both the ead Enable () and rite Enable () inputs must be in the HIGH state during the window shown in Figure 2, (i.e., tss before the rising edge of S ) and should not change until ts after the rising edge of S. Half-Full Flag (HF) will be reset to HIGH after eset (S). ITE ENABLE () A write cycle is initiated on the falling edge of this input if the Full Flag () is not set. Data setup and hold times must be adhered to with respect to the rising edge of the rite Enable (). Data is stored in the AM array sequentially and independently of any ongoing read operation. After half of the memory is filled and at the falling edge of the next write operation, the Half-Full Flag (HF) will be set to LO and will remain set until the difference between the write pointer and read pointer is less than or equal to one half of the total memory of the device. The Half-Full Flag (HF) is then reset by the rising edge of the read operation. To prevent data overflow, the Full Flag () will go LO, inhibiting further write operations. Upon the completion of a valid read operation, the Full Flag () will go HIGH after t, allowing a valid write to begin. hen the FIFO is full, the internal write pointer is blocked from, so external changes in will not affect the FIFO when it is full. EAD ENABLE () A read cycle is initiated on the falling edge of the ead Enable () provided the Empty Flag () is not set. The data is accessed on a First-In/First-Out basis, independent of any ongoing write operations. After ead Enable () goes HIGH, the Data Outputs (Q0 Q8) will return to a high impedance condition until the next ead operation. hen all data has been read from the FIFO, the Empty Flag () will go LO, allowing the final read cycle but inhibiting further read operations with the data outputs remaining in a high impedance state. Once a valid write operation has been accomplished, the Empty Flag () will go HIGH after t and a valid ead can then begin. hen the FIFO is empty, the internal read pointer is blocked from so external changes in will not affect the FIFO when it is empty. FIST LOAD/ETANSMIT (FL/T) This is a dual-purpose input. In the Depth Expansion Mode, this pin is grounded to indicate that it is the first loaded (see Operating Modes). In the Single Device Mode, this pin acts as the retransmit input. The Single Device Mode is initiated by grounding the Expansion In (). These FIFOs can be made to retransmit data when the etransmit Enable control (T) input is pulsed LO. A retransmit operation will set the internal read pointer to the first location and will not affect the write pointer. ead Enable () and rite Enable () must be in the HIGH state during retransmit. This feature is useful when less than 512/1,024/2,048/4,06/8,12/16,384 writes are performed between resets. The retransmit feature is not compatible with the Depth Expansion Mode and will affect the Half-Full Flag (HF), depending on the relative locations of the read and write pointers. EXPANSION IN () This input is a dual-purpose pin. Expansion In () is grounded to indicate an operation in the single device mode. Expansion In () is connected to Expansion Out (XO) of the previous device in the Depth Expansion or Daisy Chain Mode. OUTPUTS: FULL FLAG () The Full Flag () will go LO, inhibiting further write operation, when the write pointer is one location less than the read pointer, indicating that the device is full. If the read pointer is not moved after eset (S), the Full-Flag () will go LO after 512/1,024/2,048/4,06/8,12/16,384 writes to the / ////. EMPTY FLAG () The Empty Flag () will go LO, inhibiting further read operations, when the read pointer is equal to the write pointer, indicating that the device is empty. EXPANSION OUT/HALF-FULL FLAG (XO/HF) This is a dual-purpose output. In the single device mode, when Expansion In () is grounded, this output acts as an indication of a half-full memory. After half of the memory is filled and at the falling edge of the next write operation, the Half-Full Flag (HF) will be set LO and will remain set until the difference between the write pointer and read pointer is less than or equal to one half of the total memory of the device. The Half-Full Flag (HF) is then reset by using rising edge of the read operation. In the Depth Expansion Mode, Expansion In () is connected to Expansion Out (XO) of the previous device. This output acts as a signal to the next device in the Daisy Chain by providing a pulse to the next device when the previous device reaches the last location of memory. DATA OUTPUTS (Q0 Q8) Data outputs for -bit wide data. This data is in a high impedance condition whenever ead () is in a HIGH state. 4

5 ///// 3.3V ASYNCHONOUS FIFO COMMECIAL AND INDUSTIAL TEMPEATUE ANGES S ts tsc tss tss ts HF, tl thfh, th 3033 drw 04 NOTES: 1.,, HF may change status during eset, but flags will be valid at tsc. 2. and = VIH around the rising edge of S. Figure 2. eset ta tc t tp ta tlz tdv thz Q0-Q8 DATA OUT VALID DATA OUT VALID tp tc t tds tdh D0-D8 DATA IN VALID DATA IN VALID 3033 drw 05 Figure 3. Asynchronous rite and ead Operation LAST ITE IGNOED ITE FIST EAD ADDITIONAL EADS FIST ITE t t 3033 drw 06 Figure 4. Full Flag From Last rite to First ead 5

6 ///// 3.3V ASYNCHONOUS FIFO COMMECIAL AND INDUSTIAL TEMPEATUE ANGES LAST EAD IGNOED EAD FIST ITE ADDITIONAL ITES FIST EAD t t ta DATA OUT VALID VALID 3033 drw 07 Figure 5. Empty Flag From Last ead to First rite T ttc tt, ttf tts tt HF,, FLAG VALID Figure 6. etransmit 3033 drw 08 t tpe Figure 7. Minimum Timing for an Empty Flag Coincident ead Pulse 3033 drw 0 t tpf 3033 drw 10 Figure 8. Minimum Timing for a Full Flag Coincident rite Pulse 6

7 ///// 3.3V ASYNCHONOUS FIFO COMMECIAL AND INDUSTIAL TEMPEATUE ANGES thf thf HF HALF-FULL O LESS MOE THAN HALF-FULL HALF-FULL O LESS 3033 drw 11 Figure. Half-Full Flag Timing ITE TO LAST PHYSICAL LOCATION EAD FOM LAST PHYSICAL LOCATION t XOL t XOH t XOL t XOH XO 3033 drw 12 Figure 10. Expansion Out t t ts ITE TO FIST PHYSICAL LOCATION ts EAD FOM FIST PHYSICAL LOCATION 3033 drw 13 Figure 11. Expansion In 7

8 ///// 3.3V ASYNCHONOUS FIFO COMMECIAL AND INDUSTIAL TEMPEATUE ANGES OPEATING MODES: Care must be taken to assure that the appropriate flag is monitored by each system (i.e. is monitored on the device where is used; is monitored on the device where is used). For additional information, refer to Tech Note 8: Operating FIFOs on Full and Empty Boundary Conditions and Tech Note 6: Designing with FIFOs. SINGLE DEVICE MODE A single ///// may be used when the application requirements are for 512/1,024/2,048/4,06/8,12/ 16,384 words or less. These devices are in a Single Device Configuration when the Expansion In ( ) control input is grounded (see Figure 12). These FIFOs can easily be adapted to applications when the requirements are for greater than 512/1,024/2,048/4,06/8,12/16,384 words. Figure 14 demonstrates Depth Expansion using three //// /s. Any depth can be attained by adding additional / ////s. These devices operate in the Depth Expansion mode when the following conditions are met: 1. The first device must be designated by grounding the First Load ( FL ) control input. 2. All other devices must have FL in the HIGH state. 3. The Expansion Out ( XO ) pin of each device must be tied to the Expansion In ( ) pin of the next device. See Figure External logic is needed to generate a composite Full Flag ( ) and Empty Flag ( ). This requires the Oing of all s and Oing of all s (i.e. all must be set to generate the correct composite or ). See Figure The etransmit ( T ) function and Half-Full Flag ( HF ) are not available in the Depth Expansion Mode. For additional information, refer to Tech Note : Cascading FIFOs or FIFO Modules. USAGE MODES: H EXPANSION ord width may be increased simply by connecting the corresponding input control signals of multiple devices. Status flags (, and HF) can be detected from any one device. Figure 13 demonstrates an 18-bit word width by using two /////s. Any word width can be attained by adding additional /////s (Figure 13). BIDIECTIONAL OPEATION Applications which require data buffering between two systems (each system capable of ead and rite operations) can be achieved by pairing /////s as shown in Figure 16. Both Depth Expansion and idth Expansion may be used in this mode. DATA FLO-THOUGH Two types of flow-through modes are permitted, a read flow-through and write flow-through mode. For the read flow-through mode (Figure 17), the FIFO permits a reading of a single word after writing one word of data into an empty FIFO. The data is enabled on the bus in (t + ta) ns after the rising edge of, called the first write edge, and it remains on the bus until the line is raised from LO-to-HIGH, after which the bus would go into a three-state mode after thz ns. The line would have a pulse showing temporary deassertion and then would be asserted. In the write flow-through mode (Figure 18), the FIFO permits the writing of a single word of data immediately after reading one word of data from a full FIFO. The line causes the to be deasserted but the line being LO causes it to be asserted again in anticipation of a new data word. On the rising edge of, the new word is loaded in the FIFO. The line must be toggled when is not asserted to write new data in the FIFO and to increment the write pointer. 8

9 ///// 3.3V ASYNCHONOUS FIFO COMMECIAL AND INDUSTIAL TEMPEATUE ANGES (HALF-FULL FLAG) (HF) ITE () DATA IN (D) FULL FLAG () ESET (S) EAD () DATA OUT (Q) EMPTY FLAG () ETANSMIT (T) EXPANSION IN () 3033 drw 14 Figure 12. Block Diagram of Single FIFO HF HF 18 DATA IN (D) ITE () FULL FLAG () ESET (S) EAD () EMPTY FLAG () ETANSMIT (T) 18 DATA OUT(Q) 3033 drw 15 Figure 13. Block Diagram of 512 x 18, 1,024 x 18, 2,048 x 18, 4,06 x 18, 8,12 x 18 and 16,384 x 18 FIFO Memory Used in idth Expansion Mode TABLE 1 ESET AND ETANSMIT Single Device Configuration/idth Expansion Mode Inputs Internal Status Outputs Mode S T ead Pointer rite Pointer HF eset 0 X 0 Location Zero Location Zero etransmit Location Zero Unchanged X X X ead/rite Increment (1) Increment (1) X X X NOTE: 1. Pointer will increment if flag is HIGH

10 ///// 3.3V ASYNCHONOUS FIFO COMMECIAL AND INDUSTIAL TEMPEATUE ANGES TABLE 2 ESET AND FIST LOAD TUTH TABLE Depth Expansion/Compound Expansion Mode Inputs Internal Status Outputs Mode S FL ead Pointer rite Pointer eset First Device 0 0 (1) Location Zero Location Zero 0 1 eset All Other Devices 0 1 (1) Location Zero Location Zero 0 1 ead/rite 1 X (1) X X X X NOTE: 1. is connected to XO of previous device. See Figure 14. S = eset Input, FL/T = First Load/etransmit, = Empty Flag Output, = Full Flag Output, = Expansion Input, HF = Half-Full Flag Output D XO Q FL VCC FULL XO FL EMPTY S XO FL Figure 14. Block Diagram of 1,536 x, 3,072 x, 6,144 x, 12,288 x, 24,576 x and 4,152 x FIFO Memory (Depth Expansion) Q0-Q8 Q-Q17 Q(N-8)-QN,, S /// // DEPTH EXPANSION BLOCK /// // DEPTH EXPANSION BLOCK /// // DEPTH EXPANSION BLOCK D0-D8 D-D17 D(N-8)-DN D0-DN NOTES: 1. For depth expansion block see section on Depth Expansion and Figure For Flag detection see section on idth Expansion and Figure 13. Figure 15. Compound FIFO Expansion 3033 drw 17 10

11 ///// 3.3V ASYNCHONOUS FIFO COMMECIAL AND INDUSTIAL TEMPEATUE ANGES A A DA A B QB 0-8 B HF B SYSTEM A SYSTEM B A HFA A QA 0-8 DB 0-8 B B 3033 drw 18 Figure 16. Bidirectional FIFO Mode DATA IN tpe tlz t ta t DATA OUT DATA OUTVALID 3033 drw 1 Figure 17. ead Data Flow-Through Mode tpf t t tdh DATA IN t A DATA IN VALID tds DATA OUT DATA OUT VALID 3033 drw 20 Figure 18. rite Data Flow-Through Mode 11

12 ODEING INFOMATION XXXXX X XXX X X X X Device Type Power Speed Package Process/ Temperature ange Blank 8 Tube or Tray Tape and eel Blank I (1) Commercial (0 C to +70 C) Industrial (-40 C to +85 C) G (2) Green J Plastic Leaded Chip Carrier (PLCC, J32-1) L Commercial Only Com'l and Ind'l Commercial Only Low Power 512 x FIFO 1,024 x FIFO 2,048 x FIFO 4,06 x FIFO 8,12 x FIFO 16,384 x FIFO Access Time (ta) Speed in Nanoseconds NOTES: 1. Industrial temperature range product for the 25ns speed grade is available as a standard device. All other speed grades are available by special order. 2. Green parts are available. For specific speeds and packages contact your local sales office. LEAD FINISH (SnPb) parts are in EOL process. Product Discontinuation Notice - PDN# SP drw 21 DATASHEET DOCUMENT HISTOY 08/2/2001 pg /08/2003 pg /05/2003 pg /0/2006 pgs. 1 and /22/2008 pgs /2/2012 pgs. 1 and /27/2017 Product Discontinuation Notice - PDN# SP Last time buy expires June 15, COPOATE HEADQUATES for SALES: for Tech Support: 6024 Silver Creek Valley oad or San Jose, CA 5138 fax: FIFOhelp@idt.com 12