CPE/EE 427, CPE 527 VLSI Design I L06: Complementary CMOS Logic Gates

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1 PE/EE 427, PE 527 VLSI esign I L6: omplementary MOS Logic Gates epartment of Electrical and omputer Engineering University of labama in Huntsville leksandar Milenkovic ( ) ourse dministration Instructor: leksandar Milenkovic milenka@ece.uah.edu E 27-L Mon. 5:3 PM 6:3 PM, Wen. 2:3 3:3 PM URL: T: Joel Wilder Labs: Lab#2 posted (due 9/23/5) Text: MOS VLSI esign, 3 rd ed., Weste, Harris Review: Introduction, esign Metrics, I Fabrication (Read hapter ); I Fabrication (hapter 3) Today: MOS Non-ideal IV, MOS Inverter (hapter 2) 9/4/25 VLSI esign I;. Milenkovic 2 VLSI esign I;. Milenkovic

2 MOS Inverter VT NMOS off PMOS res NMOS sat PMOS res V out (V).5 NMOS sat PMOS sat.5 NMOS res PMOS sat NMOS res PMOS off V in (V) 9/4/25 VLSI esign I;. Milenkovic 3 eta Ratio If β p / β n, switching point will move from /2 alled skewed gate Other gates: collapse into equivalent inverter V out β p. β = n β p β = n 2.5 V in 9/4/25 VLSI esign I;. Milenkovic 4 VLSI esign I;. Milenkovic 2

3 Noise Margins How much noise can a gate input see before it does not recognize the input? Logical High Output Range Output haracteristics V OH NM H V IH V IL Input haracteristics Indeterminate Region Logical High Input Range Logical Low Output Range V OL NM L Logical Low Input Range 9/4/25 VLSI esign I;. Milenkovic 5 Logic Levels To maximize noise margins, select logic levels at V out β p /β n > V in V out V in 9/4/25 VLSI esign I;. Milenkovic 6 VLSI esign I;. Milenkovic 3

4 Logic Levels To maximize noise margins, select logic levels at unity gain point of transfer characteristic V out Unity Gain Points Slope = - V OH β p /β n > V in V out V OL V tn V IL V IH - V tp V in 9/4/25 VLSI esign I;. Milenkovic 7 MOS Inverter: Switch Model of ynamic ehavior R p V out V out L R n L V in = V in = 9/4/25 VLSI esign I;. Milenkovic 8 VLSI esign I;. Milenkovic 4

5 MOS Inverter: Switch Model of ynamic ehavior R p V out V out L R n L V in = V in = Gate response time is determined by the time to charge L through R p (discharge L through R n ) 9/4/25 VLSI esign I;. Milenkovic 9 Relative Transistor Sizing When designing static MOS circuits, balance the driving strengths of the transistors by making the PMOS section wider than the NMOS section to maximize the noise margins and obtain symmetrical characteristics 9/4/25 VLSI esign I;. Milenkovic VLSI esign I;. Milenkovic 5

6 Switching Threshold V M where V in = V out (both PMOS and NMOS in saturation since V S = V GS ) V M r /( + r) where r = k p V STp /k n V STn Switching threshold set by the ratio r, which compares the relative driving strengths of the PMOS and NMOS transistors Want V M = /2 (to have comparable high and low noise margins), so want r (W/L) p k n V STn (V M -V Tn -V STn /2) = (W/L) n k p V STp ( -V M +V Tp +V STp /2) 9/4/25 VLSI esign I;. Milenkovic Switch Threshold Example In our generic.25 micron MOS process, using the process parameters from slide L3.25, a = 2.5V, and a minimum size NMOS device ((W/L) n of.5) V T (V) γ(v.5 ) V ST (V) k (/V 2 ) λ(v - ) NMOS x -6.6 PMOS x (W/L) p (W/L) n = 9/4/25 VLSI esign I;. Milenkovic 2 VLSI esign I;. Milenkovic 6

7 Switch Threshold Example In our generic.25 micron MOS process, using the process parameters, a = 2.5V, and a minimum size NMOS device ((W/L) n of.5) NMOS PMOS V T (V) γ(v.5 ) V ST (V).63 - k (/V 2 ) 5 x -6-3 x -6 λ(v - ).6 -. (W/L) p 5 x ( /2) = x x = 3.5 (W/L) n -3 x (.25.4./2) (W/L) p = 3.5 x.5 = 5.25 for a V M of.25v 9/4/25 VLSI esign I;. Milenkovic 3 Simulated Inverter V M V M (V) ~3.4 (W/L) p /(W/L) n Note: x-axis is semilog V M is relatively insensitive to variations in device ratio setting the ratio to 3, 2.5 and 2 gives V M s of.22v,.8v, and.3v Increasing the width of the PMOS moves V M towards Increasing the width of the NMOS moves V M toward 9/4/25 VLSI esign I;. Milenkovic 4 VLSI esign I;. Milenkovic 7

8 Noise Margins etermining V IH and V IL 3 y definition, V IH and V IL are where dv out /dv in = - (= gain) V OH = V out 2 V OL = VIL V M V in piece-wise linear approximation of VT VIH NM H = -V IH NM L = V IL - pproximating: V IH = V M -V M /g V IL = V M + ( -V M )/g So high gain in the transition region is very desirable 9/4/25 VLSI esign I;. Milenkovic 5 V out (V) MOS Inverter VT from Simulation V in (V).25um, (W/L) p /(W/L) n = 3.4 (W/L) n =.5 (min size) = 2.5V V M.25V, g = V IL =.2V, V IH =.3V NM L = NM H =.2 (actual values are V IL =.3V, V IH =.45V NM L =.3V & NM H =.5V) Output resistance low-output = 2.4kΩ high-output = 3.3kΩ 9/4/25 VLSI esign I;. Milenkovic 6 VLSI esign I;. Milenkovic 8

9 Gain eterminates gain V in Gain is a strong function of the slopes of the currents in the saturation region, for V in = V M (+r) g (V M -V Tn -V STn /2)(λ n - λ p ) etermined by technology parameters, especially channel length modulation (λ). Only designer influence through supply voltage and V M (transistor sizing). 9/4/25 VLSI esign I;. Milenkovic 7 Impact of Process Variation on VT urve V out (V) ad PMOS Good NMOS Good PMOS ad NMOS Nominal V in (V) process variations (mostly) cause a shift in the switching threshold 9/4/25 VLSI esign I;. Milenkovic 8 VLSI esign I;. Milenkovic 9

10 Scaling the Supply Voltage V out (V) V in (V) evice threshold voltages are kept (virtually) constant V out (V) /4/25 VLSI esign I;. Milenkovic 9..5 Gain=- V in (V) evice threshold voltages are kept (virtually) constant Static MOS Logic VLSI esign I;. Milenkovic

11 MOS ircuit Styles Static complementary MOS - except during switching, output connected to either V or via a lowresistance path high noise margins full rail to rail swing VOH and VOL are at V and, respectively low output impedance, high input impedance no steady state path between V and (no static power consumption) delay a function of load capacitance and transistor resistance comparable rise and fall times (under the appropriate transistor sizing conditions) ynamic MOS - relies on temporary storage of signal values on the capacitance of high-impedance circuit nodes simpler, faster gates increased sensitivity to noise 9/4/25 VLSI esign I;. Milenkovic 2 Static omplementary MOS Pull-up network (PUN) and pull-down network (PN) In In 2 In N In In 2 In N PUN PN PMOS transistors only pull-up: make a connection from to F when F(In,In 2, In N ) = F(In,In 2, In N ) pull-down: make a connection from F to when F(In,In 2, In N ) = NMOS transistors only PUN and PN are dual logic networks 9/4/25 VLSI esign I;. Milenkovic 22 VLSI esign I;. Milenkovic

12 Threshold rops PUN L L PN L L 9/4/25 VLSI esign I;. Milenkovic 23 Threshold rops PUN S V GS S -V Tn L L PN L V GS S L V Tp S 9/4/25 VLSI esign I;. Milenkovic 24 VLSI esign I;. Milenkovic 2

13 onstruction of PN NMOS devices in series implement a NN function NMOS devices in parallel implement a NOR function + 9/4/25 VLSI esign I;. Milenkovic 25 ual PUN and PN PUN and PN are dual networks emorgan s theorems + = = + [!( + ) =!! or!( ) =! &!] [!( ) =! +! or!( & ) =!!] a parallel connection of transistors in the PUN corresponds to a series connection of the PN omplementary gate is naturally inverting (NN, NOR, OI, OI) Number of transistors for an N-input logic gate is 2N 9/4/25 VLSI esign I;. Milenkovic 26 VLSI esign I;. Milenkovic 3

14 MOS NN F 9/4/25 VLSI esign I;. Milenkovic 27 MOS NN Vdd NN F = NN(,) F Vdd Vdd Vdd Vdd = F= = F= = F= = F= = = = = 9/4/25 VLSI esign I;. Milenkovic 28 VLSI esign I;. Milenkovic 4

15 MOS NOR F + 9/4/25 VLSI esign I;. Milenkovic 29 MOS NOR Vdd NOR F = NOR(,) F Vdd Vdd Vdd Vdd = = = = = = = = F= F= F= F= 9/4/25 VLSI esign I;. Milenkovic 3 VLSI esign I;. Milenkovic 5

16 omplex MOS Gate OUT =!( + ( + )) 9/4/25 VLSI esign I;. Milenkovic 3 omplex MOS Gate OUT =!( + ( + )) 9/4/25 VLSI esign I;. Milenkovic 32 VLSI esign I;. Milenkovic 6

17 XNOR/XOR Implementation XNOR XOR How many transistors in each? an you create the stick transistor layout for the lower left circuit? 9/4/25 VLSI esign I;. Milenkovic 33 ombinational Logic ells MOS logic cells N-OR-INVERT (OI) OR-N-INVERT(OI) 2 Example: OI22 2 Z = (* + * + E) Z = OI22(,,,, E) Exercise: onstruct this logic cell? Example: OI32 Z = [(++)*(+E)*F] Z = OI32(,,,, E, F) Exercise: onstruct this logic cell? OI22 nd Or Inverter E Z 9/4/25 VLSI esign I;. Milenkovic 34 VLSI esign I;. Milenkovic 7

18 OI22 Vdd E E Z 9/4/25 VLSI esign I;. Milenkovic 35 Standard ell Layout Methodology Routing channel signals What logic function is this? 9/4/25 VLSI esign I;. Milenkovic 36 VLSI esign I;. Milenkovic 8

19 OI2 Logic Graph j X PUN X =!( ( + )) X i i j PN 9/4/25 VLSI esign I;. Milenkovic 37 Two Stick Layouts of!( ( + )) X X uninterrupted diffusion strip 9/4/25 VLSI esign I;. Milenkovic 38 VLSI esign I;. Milenkovic 9

20 onsistent Euler Path n uninterrupted diffusion strip is possible only if there exists a Euler path in the logic graph Euler path: a path through all nodes in the graph such that each edge is visited once and only once. X X i j For a single poly strip for every input signal, the Euler paths in the PUN and PN must be consistent (the same) 9/4/25 VLSI esign I;. Milenkovic 39 onsistent Euler Path n uninterrupted diffusion strip is possible only if there exists a Euler path in the logic graph Euler path: a path through all nodes in the graph such that each edge is visited once and only once. X X i j For a single poly strip for every input signal, the Euler paths in the PUN and PN must be consistent (the same) 9/4/25 VLSI esign I;. Milenkovic 4 VLSI esign I;. Milenkovic 2

21 OI22 Logic Graph X PUN X =!((+) (+)) X PN 9/4/25 VLSI esign I;. Milenkovic 4 OI22 Layout X Some functions have no consistent Euler path like x =!(a + bc + de) (but x =!(bc + a + de) does!) 9/4/25 VLSI esign I;. Milenkovic 42 VLSI esign I;. Milenkovic 2

22 ombinational Logic ells (cont d) The OI family of cells with 3 index numbers or less X = {OI, OI, O, O}; a,b,c={2,3} ell Type Xa Xa Xab Xab Xabc Total ells X2, X3 X2, X3 X22, X33, X32 X22, X32, X33 X222, X333, X332, X322 Number of Unique ells /4/25 VLSI esign I;. Milenkovic 43 VT is ata-ependent M 3 M 4 3.5µ/.25µ NMOS.75µ /.25µ PMOS V GS2 = V V S V GS = V M 2 S M S F= int 9/4/25 VLSI esign I;. Milenkovic 44 2 weaker PUN 2,: -> =, : -> =, :-> The threshold voltage of M 2 is higher than M due to the body effect (γ) V Tn = V Tn V Tn2 = V Tn + γ( ( 2φ F + V int ) - 2φ F ) since V S of M 2 is not zero (when V = ) due to the presence of int VLSI esign I;. Milenkovic 22

23 Static MOS Full dder ircuit in in! out!sum in in in 9/4/25 VLSI esign I;. Milenkovic 45 Static MOS Full dder ircuit! out =! in & (!!) (! &!)!Sum = out & (!!! in ) (! &! &! in ) in in! out!sum in in in out = in & ( ) ( & ) Sum =! out & ( in ) ( & & in ) 9/4/25 VLSI esign I;. Milenkovic 46 VLSI esign I;. Milenkovic 23