VLSI Design 8. Design of Adders
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1 VLI Design. Design of dders. Design of dders Last module: Designing MO gate networks peeding up combinational gates This module dder circuits imple adders Fast addition Half dder ingle-it ddition Full dder = out = out = out = MJ(,, ) out out out D. Z. Pan. Design of dders D. Z. Pan. Design of dders Full dder Design I rute force implementation from equations = out = MJ(,, ) Full dder Design II Factor in terms of out = ( )(~ out ) ritical path is usually to out in ripple adder MINORITY MJ out out out out D. Z. Pan. Design of dders D. Z. Pan. Design of dders Layout lever layout circumvents usual line of diffusion Use wide transistors on critical path Eliminate output inverters Full dder Design III omplementary Pass Transistor Logic (PL) lightly faster, but more area cf. the clever layout of II out out D. Z. Pan. Design of dders D. Z. Pan. Design of dders D. Z. Pan
2 VLI Design. Design of dders arry Propagate dders N-bit adder called P Each sum bit depends on all previous carries How do we compute all these carries quickly? Ripple arry dder implest design: cascade full adders ritical path goes from in to out Design full adder to have fast carry delay N... N... out out out in N... in in carries out in D. Z. Pan. Design of dders D. Z. Pan. Design of dders Inversions ritical path passes through majority gate uilt from minority inverter Eliminate inverter and use inverting full adder out in PGK For a full adder, define what happens to carries Generate: out = independent of G = Propagate: out = P = Kill: out = independent of K = ~ ~ (i.e., ~K = ) D. Z. Pan. Design of dders D. Z. Pan. Design of dders Generate / Propagate PG Logic Equations often factored into G and P Generate and propagate for groups spanning G = G P G i: j i: k i: k k : j P = P P i: j i: k k : j ::ing G P G P G P G P in : itwise PG logic G P : Group PG logic ase case G : G : G : G : G G = um: ii : i i i P P = ii : i i i = P G i i i : G: G = in P: P = out : um logic D. Z. Pan. Design of dders D. Z. Pan. Design of dders D. Z. Pan
3 VLI Design. Design of dders Ripple arry Revisited Ripple arry PG Diagram G = G P G i: i i i : it Position in t = t ( N ) t t ripple pg O xor G P G P G P G P G P Delay G : G : G : G : out : : : : : : : : : : : : : : : : D. Z. Pan. Design of dders D. Z. Pan. Design of dders PG Diagram Notation lack cell Gray cell uffer i:k k-:j i:k k-:j arry-kip dder Ripple carry is slow through all N stages arry-skip allows carry to skip over groups of n bits Decision based on n-bit propagate signal : : : : : : : : P : P : P : P : G i:k P i:k G k-:j G G i:k P i:k G G k-:j G G out : : : : in P k-:j P P P D. Z. Pan. Design of dders D. Z. Pan. Design of dders arry-kip PG Diagram Variable Group ize : : : : : : : : : : : : : : : : : For k n-bit groups (N = nk) ( ) tskip = tpg n ( k ) to t xor : : : : : : : : : : : : : : : : : Delay grows as O(sqrt(N)) D. Z. Pan. Design of dders D. Z. Pan. Design of dders D. Z. Pan
4 VLI Design. Design of dders arry-lookahead dder L PG Diagram arry-lookahead adder computes G i: for many bits in parallel Uses higher-valency cells with more than two inputs : : : : : : : : out G : G : G : G : P : P : P : P : in : : : : : : : : : : : : : : : : : : : : : D. Z. Pan. Design of dders D. Z. Pan. Design of dders Higher-Valency ells arry-elect dder i:k k-:ll-:m m-:j G i:k P i:k G k-:l P k-:l G l-:m P l-:m G Trick for critical paths dependent on late input X Precompute two possible outputs for X =, elect proper output when X arrives arry-select adder precomputes n-bit sums For both possible carries into n-bit group G m-:j : : : : : : : : P m-:j P out in : : : : D. Z. Pan. Design of dders D. Z. Pan. Design of dders arry-increment dder Variable Group ize Factor initial PG and final XOR out of carryselect lso buffer noncritical signals : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : ( ) tincrement = tpg n ( k ) to t xor : : : : : : : : : : : : : : : : : : : : : : : : D. Z. Pan. Design of dders D. Z. Pan. Design of dders D. Z. Pan
5 VLI Design. Design of dders Tree dder rent-kung If lookahead is good, lookahead across lookahead! Recursive lookahead gives O(log N) delay Many variations on tree adders : : : : : : : : : : : : : : : : : : :::::: : : : : : : : : : : D. Z. Pan. Design of dders D. Z. Pan. Design of dders klansky Kogge-tone : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : :::::: : : : : : : : : : : :::::: : : : : : : : : : : D. Z. Pan. Design of dders D. Z. Pan. Design of dders Tree dder Taxonomy Tree dder Taxonomy Ideal N-bit tree adder would have L = log N logic levels Fanout never exceeding No more than one wiring track between levels Describe adder with -D taxonomy (l, f, t) Logic levels: L l Fanout: f Wiring tracks: t Known tree adders sit on plane defined by l f t = L- f (Fanout) () () () () () () () () () t (Wire Tracks) () () () l (Logic Levels) D. Z. Pan. Design of dders D. Z. Pan. Design of dders D. Z. Pan
6 : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : :::::: : : : : : : : : : : : : : :::::: : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : :::::: : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : :::::: : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : VLI Design. Design of dders Tree dder Taxonomy Han-arlson () l (Logic Levels) f (Fanout) klansky () rent-kung () () () : : : : : : : : () () () () : : : : : : : () : : : : : : () Kogge-tone () t (Wire Tracks) D. Z. Pan. Design of dders :::::: : : : : : : : : : : D. Z. Pan. Design of dders Knowles [,,, ] Ladner-Fischer : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : :::::: : : : : : : : : : : :::::: : : : : : : : : : : D. Z. Pan. Design of dders D. Z. Pan. Design of dders (b) klansky f (Fanout) klansky () () (e) Knowles [,,,] (c) Kogge-tone Taxonomy Revisited Knowles [,,,] l (Logic Levels) (a) rent-kung (f) Ladner-Fischer (d) Han-arlson t (Wire Tracks) :::::: : : : : : : : : : : D. Z. Pan. Design of dders ummary dder architectures offer area / power / delay tradeoffs. hoose the best one for your application. rchitecture Ripple arry arry-kip n= arry-inc. n= rent-kung klansky Kogge-tone Tracks lassification (L-,, ) (, L-, ) (,, L-) Logic Levels N- N/ N/ log N log N log N Max Fanout N/ Han- arlson Knowles [,,,] () Kogge- () tone rent- Kung Ladner- Fischer () Ladner- Fischer () () () () () Han- () arlson New (,,) () N/. Nlog N Nlog N D. Z. Pan. Design of dders ells N.N N N D. Z. Pan
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