Physical Design of CMOS Integrated Circuits

Transcription

1 Physical Design of CMOS Integrated Circuits Dae Hyun Kim EECS Washington State University

2 References John P. Uyemura, Introduction to VLSI Circuits and Systems, Chapter 5

3 Goal Understand how to physically design (manually draw) CMOS integrated circuits (ICs)

4 Custom Design Flow Design specification An inverter (spec: width, height,...) Schematic design (Transistor-level netlist) xx ff = xx Layout (physical) design DRC (Design Rule Check) LVS (Layout vs. Schematic) RC extraction SPICE-level netlist Characterization Timing/power info. Library

5 Schematic Editor Cadence Virtuoso Source: d schematic-jpg?s=a9af c1b713b17c65f4be

6 Layout Editor Cadence Virtuoso Source: tools/custom-ic-analog-rf-design/virtuoso-zambebi-xl-600px.jpg/_jcr_content/renditions/original.img.png

7 Layout Design Draw polygons (rectilinear objects) in each layer Rectangles Paths Layers (Real) n-well p-well Active (n+ = ndiff) Active (p+ = pdiff) Poly Contact Metal (m1, m2, m3,...) Via (v12, v23, v34,...) Layers (Virtual) Cell boundary Labels Pins + + Metal 1 VDD, VSS, A, Z

8 Inverter Substrate contact M3 M2 M1 p+ n+ n+ p+ p+ n+ n-well p-epi substrate Substrate contact

9 Design Rules Poly

10 Design Rules Implant

11 Design Rules Active

12 Design Rules Contact

13 Design Rules Metal 1

14 Design Rules Via12

15 Layouts INV_X1, INV_X2, INV_X4, INV_X8

16 Layouts INV_X8, INV_X16, INV_X32

17 Layouts NAND2_X1, NOR2_X1

18 Layouts BUF_X1, BUF_X2, BUF_X4

19 Layouts AND2_X1, AND3_X1, AND4_X1

20 Layouts XOR2_X1, XNOR2_X1

21 Layouts MUX2_X1

22 Layouts FA_X1 (Full adder)

23 Layouts DFF_X1 (D F/F)

24 Transistor Folding (A Layout Technique) INV_X16

25 Layout Generation Draw a layout. Output: GDSII format Design rule check (DRC) Prepare a schematic (netlist). A text file Layout vs. Schematic (LVS) Layout netlist 1 Schematic netlist 2 LVS checks whether netlist 1 is equal to netlist 2. Parasitic RC extraction Output: A SPICE netlist with parasitic RC Timing/power simulation and characterization

26 Channel Length and Width LL eeeeee = LL LL LL eeeeee : effective channel length LL: drawn channel length WW eeeeee = WW WW Poly LL LL eeeeee G WW (Drawn) n+ n+ LL eeeeee p LL (Drawn)

27 Terminologies Twin-tub technology Two separate wells are created. Latch-up n-well for pfets p-well for nfets Source:

28 Digital VLSI Design Placement Places transistors in a layout. Routing Power/Ground Clock Connect all the VV DDDD lines to VV DDDD. Connect all the VV SSSS lines to VV SSSS. Reduce IR drop. Connect all the clock sinks to a main clock source pin. Achieve zero skew. Signal

29 Standard Cell-Based Digital VLSI Design Power/Ground routing Die area (Layout) I/O cells Metal 1 Metal 2 Core area Power (Outer ring) Ground (Inner ring) Gound Power

30 Standard Cell-Based Digital VLSI Design Via1

31 Standard Cell-Based Digital VLSI Design Standard cells have a fixed height. have different widths. have ports (input/output pins) generally in the Metal 1 layer. have some obstacles in the Metal 1 layer (for internal routing). Routing uses only metal and via layers (doesn t use any other layers). routes the standard cell ports and primary I/O ports based on a given netlist.

32 Standard Cell-Based Digital VLSI Design BUF_X1 VDD port Cell boundary Obstruction (M1) A (input, M1) Z (output, M1) VSS port Layout

33 Automatic Placement

34 Automatic Routing

35 FET Sizing Theory II μμ cc oooo 11 WW LL (VV GG VV TT ) VV DDDD RR = LL ββ (VV GG VV TT ) WW Motivation 1 pfets and nfets have different mobility values. μμ nn > μμ pp Thus, if an nfet and a pfet networks have the same transistor sizes, their delay values are different. Motivation 2 Minimum-size FETs might not provide enough drive strength. Goal Achieve perfectly-balanced delay values (from Motivation 1). Satisfy delay constraints (from Motivation 2). Mobility ratio μμ nn = rr μμ pp (rr > 11) RR pp = rr RR nn

36 FET Sizing Theory II μμ cc oooo 11 WW LL (VV GG VV TT ) VV DDDD RR = LL ββ (VV GG VV TT ) WW The drive strength (current) is proportional to WW inversely proportional to LL The input capacitance is proportional to LL and WW. If LL increases The input capacitance goes up. The drive strength goes down (or the output resistance goes up). The cell area goes up. Thus, do not increase LL (i.e., use the minimum channel length). If WW increases The input capacitance goes up. The drive strength goes up (or the output resistance goes down). The cell area goes up. If the input capacitance overhead is small, upsizing FETs reduces the delay of the downstream net.

37 FET Sizing Theory The FET width cannot be reduced infinitely (design rules). Suppose the minimum transistor length and width are LL 0 and WW 0, respectively. Then, Minimum-size nfet = WW 0 LL 0 Resistance: RR nn Minimum-size pfet = WW 0 LL 0 Resistance: RR pp Transistor upsizing If the size of an nfet is kk WW 0 LL 0 Resistance: RR nn kk If the size of a pfet is kk WW 0 LL 0 Resistance: RR pp kk nn : This is a 1X nfet. pp : This is a 1X pfet. nn, it is a kkx nfet. pp, it is a kkx pfet.

38 FET Sizing (Matching) Example: Inverter μμ nn = 22 μμ pp (i.e., RR pp = 2RR nn ) VV iiii 1X VV iiii = 1 VV iiii = 0 RR = RR pp = 2RR nn 1X CC RR = RR nn CC CC Time constant ττ = RR nn CC ττ = 2RR nn CC VV iiii 2X VV iiii = 1 VV iiii = 0 RR = RR pp 2 = RR nn 1X CC RR = RR nn CC CC Minimum-size inverter ττ = RR nn CC ττ = RR nn CC

39 FET Sizing (Delay Reduction) Example: Inverter μμ nn = 22 μμ pp (i.e., RR pp = 2RR nn ) VV iiii 2X 1X VV iiii = 1 VV iiii = 0 RR = RR pp 2 = RR nn CC RR = RR nn CC CC 1X inverter ττ = RR nn CC ττ = RR nn CC VV iiii 4X 2X 2X inverter VV iiii = 1 VV iiii = 0 RR = RR pp 4 = RR nn 2 CC RR = RR nn CC CC 2 ττ = RR nn 2 CC ττ = RR nn 2 CC

40 FET Sizing NAND2_X1, NOR2_X1 aa 2X bb 2X aa 4X aa 2X bb 4X bb 2X aa 1X bb 1X FETs are sized for the worst-case signal path.

41 FET Sizing ff = aa + bb cc (1X) bb 4X cc 4X aa 4X aa 1X bb cc 2X 2X

42 FET Sizing Analytical Approach NAND2_X1 pfets: Each should be 2X. nfets If aa is upsized to xx 1 X and bb is upsized to xx 2 X (xx 1, xx 2 > 1) Resistance of aa: RR nn xx 1 Resistance of bb: RR nn xx 2 The total resistance should be RR nn. aa 2X bb 2X RR nn xx 1 + RR nn xx 2 = RR nn 1 xx xx 2 = 1 aa xx 1 X For instance, xx 1, xx 2 = 2,2, 3, 3 2, 4, 4 3, We want to minimize the total area. bb xx 2 X Min. xx 1 + xx 2

43 FET Sizing Analytical Approach Problem Minimize ff xx 1, xx 2 = xx 1 + xx 2 under the following constraints. Solve xx 1, xx 2 > = 1 xx 1 xx = 1 xx xx 1 xx 2 = xx 1 2 xx 1 1 ff xx 1, xx 2 = xx 1 + xx 2 = xx 1 + xx 1 = ff xx xx = xx 2 1 xx 1 1 ff xx 1 = 2xx 1 xx 1 1 xx 2 1 = xx 1 2 2xx 1 (xx 1 1) 2 (xx 1 1) 2 Thus, ff is minimized when xx 1 = 2. In this case, xx 2 is also 2.

44 FET Sizing Analytical Approach NAND_Xnn (nn-input NAND gate) pfets: Each should be 2X. nfets If aa ii is upsized to xx ii X (xx ii > 1) Resistance of aa ii : RR nn xx ii The total resistance should be RR nn. nn RR nn ii=1 = RR nn = 1 xx 1 xx 2 xx nn xx ii We want to minimize the total area. nn Min. xx ii = xx 1 + xx xx nn ii=1 aa 1 2X aa 2 aa 1 aa 2 2X xx 1 X xx 2 X aa nn 2X aa nn xx nn X

45 FET Sizing Analytical Approach Problem Minimize ff xx 1, xx 2,, xx nn = xx 1 + xx xx nn under the following constraints. Solve xx ii > = 1 xx 1 xx 2 xx nn Let 1 xx ii = yy ii. Then, the problem becomes as follows: Minimize ff yy 1,, yy nn = 1 yy yy nn yy ii < 1 yy 1 + yy nn = 1 yy nn = 1 (yy yy nn 1 ) ff yy 1,, yy nn = = ff yy yy 1 yy 1,, yy nn 1 = nn yy 1 yy nn 1 Solve ff = 0,, = 0. yy 1 yy nn 1 = yy ii yy 2 2 = 0 ii 1 yy 1 + +yy nn (yy 1 + +yy nn 1 ) yy ii = 1 (yy yy nn 1 ) yy ii = yy nn Thus, ff is minimized when yy 1 = yy 2 = = yy nn, i.e., xx 1 = xx 2 = = xx nn. As a result, xx 1 = xx 2 = = xx nn = nn.