Philips SAA7118E Multi Standard Video Decoder Process Review

Transcription

1 March 31, 2006 Philips SAA7118E Multi Standard Video Decoder Process Review For comments, questions, or more information about this report, or for any additional technical needs concerning semiconductor technology, please call Sales at Chipworks Richmond Road, Suite 500, Ottawa, ON K2H 5B7, Canada Tel: Fax:

2 Process Review Table of Contents 1 Overview 1.1 List of Figures 1.2 List of Tables 1.3 Company Profile 1.4 Introduction 1.5 Device Summary 1.6 Process Summary 2 Device Overview 2.1 Package and Die 2.2 Die Features 3 Process Analysis 3.1 General Device Structure 3.2 Bond Pads 3.3 Dielectrics 3.4 Metallization 3.5 Vias and Contacts 3.6 Transistors and Poly 3.7 Capacitors and PNP Substrate Transistor 3.8 Isolation 3.9 Wells and Substrate 4 6T-SRAM 4.1 6T-SRAM Overview 4.2 6T-SRAM Plan-View Analysis (4311 Date Code) 4.3 Cross-Sectional Analysis (Parallel to Word Line, 4341 Date Code) 5 8T Dual Port SRAM Cell Analysis (4311 Date Code) 5.1 8T-SRAM Overview 5.2 8T-SRAM Plan-View Analysis 6 ROM Cell Analysis (4311 Date Code) 6.1 Plan-View Analysis 6.2 Cross-Sectional Analysis (Parallel to Bit Line, 4311 Date Code)

3 Process Review 7 Critical Dimensions 7.1 Horizontal Dimensions 7.2 Vertical Dimensions Report Evaluation

4 Overview Overview 1.1 List of Figures 2 Device Overview Top Package View (ks04341 Date Code) Top Package View (TS04311 Date Code) Bottom Package View Package X-Ray (Top-View) SAA7118E Die Die Markings Die Markings Die Markings Die Corner Die Corner Die Corner Die Corner Bond Pads Resistors and Capacitors Substrate PNP Transistor NAND Gate 3 Process Analysis General View of SAA7118E (4341 Date Code) General View of Second SAA7118E (4311 Date Code) Die Edge Die Seal Structure Bond Pad Bond Pad Edge Passivation IMD IMD IMD IMD PMD (4341 Date Code) PMD (4311 Date Code) Nitride Mask Layer (4341 Date Code) Nitride Mask in ROM Minimum Pitch Metal Minimum Pitch Metal Minimum Pitch Metal Minimum Pitch Metal Minimum Pitch Metal 1 (4341 Date Code) Metal 1 and PMD (4311 Date Code) Minimum Pitch Via 4s Minimum Pitch Via 3s Via 2s

5 Overview Via 1s Minimum Pitch Contacts to Diffusion Contacts (Glass-Etch) Contacts to Polycide Minimum Gate Length NMOS Transistor Minimum Gate Length PMOS Transistor Transistor Glass-Etch Minimum Pitch Polycide NMOS I/O and Logic Transistors NMOS I/O Transistor I/O Transistor (Glass-Etch) Double Poly Capacitor (4311 Date Code) Capacitor Edge (4311 Date Code) Vertical PNP Transistor Emitter Contact SCM Vertical PNP Transistor Poly Over Isolation Minimum Width Isolation ROM N-Well SCM N-Well SRP Measurement Areas SRP P-Well (Filled Area) P-Well (Logic) SRP Peripheral N-Well 4 6T-SRAM T-SRAM Schematic T-SRAM at Metal Metal 2 V SS Buses and Bit Lines Metal 1 Local Interconnects SRAM at Poly SRAM Gates SRAM at Diffusion Active Silicon SRAM Cell in Cross-Section NMOS Pull-Down Transistors 5 8T Dual Port SRAM Cell Analysis (4311 Date Code) T-SRAM Cell Metal 3 Power Buses and Bit Lines Metal 2 V SS Power Buses and Word Lines Metal 1 Local Interconnects SRAM Cell at Poly SRAM Gates SRAM at Diffusion

6 Overview ROM Cell Analysis (4311 Date Code) Metal 2 Word Line Straps Metal 1 Bit Lines ROM at Poly Optical Plan-View Image of ROM at Metal ROM at Diffusion ROM Cell Word and Source Lines SCM ROM Cell

7 Overview List of Tables 1 Overview Device Summary Process Summary 3 Process Analysis Dielectric Thicknesses (4341 Date Code) Metallization Vertical Dimensions (4341 Date Code) Metallization Horizontal Dimensions (4341 Date Code) Via and Contact Dimensions (4341 Date Code) Transistor and Polycide Dimensions (4341 Date Code) 4 6T-SRAM T-SRAM Dimensions 5 8T Dual Port SRAM Cell Analysis (4311 Date Code) T-SRAM Transistor Sizes 7 Critical Dimensions Minimum Pitch Metals Contacts and Vias Die, Transistors, Poly and Isolation Vertical Dimensions

8 About Chipworks Chipworks is the recognized leader in reverse engineering and patent infringement analysis of semiconductors and electronic systems. The company s ability to analyze the circuitry and physical composition of these systems makes them a key partner in the success of the world s largest semiconductor and microelectronics companies. Intellectual property groups and their legal counsel trust Chipworks for success in patent licensing and litigation earning hundreds of millions of dollars in patent licenses, and saving as much in royalty payments. Research & Development and Product Management rely on Chipworks for success in new product design and launch, saving hundreds of millions of dollars in design, and earning even more through superior product design and faster launches. Contact Chipworks To find out more information on this report, or any other reports in our library, please contact Chipworks at: Chipworks 3685 Richmond Rd. Suite 500 Ottawa, Ontario K2H 5B7 Canada T: F: Web site: info@chipworks.com Please send any feedback to feedback@chipworks.com