The Future of Field-Programmable Gate Arrays
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1 The Future of Field-Programmable Gate Arrays Peter Alfke Director, Applications Engineering Xilinx, Inc PA Snowmass 9/99 1
2 The future is exciting Le future est formidable Die Zukunft ist rosig Il futuro é fantastico El futuro es formidable Framtiden är fantastisk PA Snowmass 9/99 2
3 Why Programmable Logic? Ideal for customized designs Offers the advantages of high integration complexity, density, size cost, power consumption, reliability Avoids the problems of ASICs high NRE cost and long delay testing problems increasingly complex electrical issues PA Snowmass 9/99 3
4 Programmable Logic SPLDs (Simple Pogrammable Logic Devices =PALs) $ 227 M, shrinking rapidly = 12% of a $1.955B market, CPLDs (Complex Programmable Logic Devices) $ 688 M = 35% FPGAs (Field-Programmable Gate Arrays) Anti-fuse-based FPGAs $ 183 M = 9% SRAM-based FPGAs $ 859 M =44%, growing fast PA Snowmass 9/99 4
5 CPLDs AND-OR Structure, derived from PALs Advantages fast pin-to-pin delays, wide input decoding simple software, easy to understand Disadvantages low complexity, few flip-flops not scalable in size high static power consumption ( except CoolRunner ) PA Snowmass 9/99 5
6 Anti-Fuse Based FPGAs Gate-Array-like structure Advantages: non-volatile, single-chip, instant-on logic circuits tolerate radiation, but flip-flops are SEU-sensitive Disadvantages one-time programmable, slow programming limited complexity, slow process evolution second-tier suppliers, niche market PA Snowmass 9/99 6
7 SRAM-based FPGAs Gate-Array-like structure look-up-table logic, medium granularity configured by latches and pass-transistors Advantages highest complexity, many flip-flops re-configurable, rapid evolution (standard process) main-stream market, major suppliers Disadvantages Volatile, configuration is radiation-sensitive PA Snowmass 9/99 7
8 Design Alternatives Microprocessors ideal, if fast enough Gates, MSI, PALs inefficient, inflexible, outdated Dedicated Standard Chips and Chip Sets cheap, but inflexible ASICs only for rock-stable, very high-volume designs Programable Logic for flexibility, reconfigurability, fast time-to-market PA Snowmass 9/99 8
9 ASICs Getting Less Attractive Non-Recurring Engineering cost increases more masking steps, more expensive masks Minimum order quantities increase larger wafers, smaller die Silicon capability often exceeds user needs Suppliers abandon unprofitable market Low-tech ASICs have lost their technical advantage over FPGAs PA Snowmass 9/99 9
10 User Expectations Logic capacity at reasonable cost 50,000 to a million gates Clock speed 100 MHz and above Design effort and time synthesis, fast compile times, tested and proven cores Power consumption must stay within reasonable limits PA Snowmass 9/99 10
11 FPGA History (XC4000) w > 20x Bigger Capacity Speed Price w > 5x Faster w > 50x Cheaper 1 1/91 1/92 1/93 1/94 1/95 Year PA Snowmass 9/ /96 1/97 1/98 1/99
12 FPGA Density 50M 50M Gates Density (system gates) 10M 4M Virtex 0.15µ 2M 1M Virtex V million Transistors Virtex 0.18µ Virtex 0.13µ 500K XC40250XV PA Snowmass 9/ Million System Gates in 2004
13 FPGA Speed System Clock Rate* (MHz) MHz D-P Memory 143 MHz ZBT SRAM I/F 155 MHz SONET 125 MHz SDRAM I/F 66 MHz 64-bit PCI PA Snowmass 9/99 13 *1/(Tsetup+Tclock-to-out)
14 Three Pillars of Progress Technology smaller geometries, more and faster transistors better defect densities, larger chips Architecture system features: Memory, clocks, I/O hierarchical interconnect Design Methodology powerful and reliable cores, faster compile time modular, team-based design, internet-based tools PA Snowmass 9/99 14
15 Recent Developments Deep sub-micron arrived earlier than expected 0.5µ µ µ µ - (0.15µ) - Better speed, density, cost for free Requires voltage migration 5V - 3.3V - 2.5V - 1.8V - (1.5V) - PA Snowmass 9/99 15
16 Process Technology Evolution Feature Size (micron) V V 1.5V 1.3V V V0.8V 5V 3.3V PA Snowmass 9/99 16
17 Cutting-Edge Technology FPGA technology is in step with microprocessors, and benefits directly from their fast evolution 0.18 micron now, 0.15 in development Clear roadmap to 0.13, even 0.10 micron Copper technology in 2000 Copper with low-k dielectric in 2001 PA Snowmass 9/99 17
18 FPGA Packages Pins 1000 Flip Chip Technology 700 Chip Scale 0.8 mm FinePitch BGA 1.0 mm SBGA 500 HQFP BGA 1.0mm FinePitch BGAs PLCC PGA PQFP 1.27mm PA Snowmass 9/99 18
19 A System-Level Solution Not Just a High Density Device 2 System Memory 1 System Integration 3 System Timing 4 System Interfaces PA Snowmass 9/99 19
20 The FPGA Solution 4th Generation FPGA Logic+Memory+Routing Delay-Locked Loop for Fast Clock and I/O Multi-Standard Select I/O 3.3 ns Synchronous Dual-Port SRAM Temperature Sensing 500 Mbps SelectMAP Configuration PA Snowmass 9/99 20
21 Memory Three-level memory hierarchy: distributed 4-input look-up-table RAMs 16-bit single- and dual-port RAM 16-bit shift register in Virtex versatile dual-port BlockRAMs 4k x 1 to 256 x 16 format, selectable per port 200 MHz interface to large external RAMs PA Snowmass 9/99 21
22 High Performance Clock Networks Manage up to 4 System Clocks DLL1 DLL3 Deskew Clocks on Chip Generate Clocks - multiply - divide - shift DLL2 DLL4 Cascade DLLs 4 DLLs in each Virtex Device Deskew Clocks on Board Convert Clock Levels using SelectI/O Delay Locked Loops Synchronize on-chip and board level clocks PA Snowmass 9/99 22
23 Multi-Standard Select I/O GTL+ 2.5V SSTL MicroProcessor SRAM 1.8V 5V Tolerant SDRAM Mixed Signal FLASH 3.3V LVTTL 5V Busses/Backplanes (3/5V PCI, ISA, GTL ) DSP PA Snowmass 9/99 23
24 Virtex Supports 17 I/O Standards Chip to Chip LVTTL, LVCMOS SDRAM SSTL HSTL Chip to Memory SSTL2-I, SSTL2-II, SSTL3-I, SSTL3-II, HSTL-I, HSTL-III, HSTL-IV, CTT SRAM CTT GTL+ LVTTL LVCMOS Chip to Backplane PCI66, PCI33-5V, PCI33 3.3V, GTL, GTL+, AGP Select I/O TM Technology Any standard on any pin Multiple standards at once PA Snowmass 9/99 24
25 Interconnect Hierarchy Segmented interconnect structure reduces load capacitance and power consumption Four high-drive low-skew clock nets each can drive all flip-flops and registers each can be driven by its own DLL 24 additional low-skew global nets Horizontal bi-directional longlines Segmented lines between logic blocks PA Snowmass 9/99 25
26 Programmable System Hardware Programmable Example Custom Logic Inherently Programmable Clock Mgmt 100MHz System Performance Cache Memory Translators SDRAM SSTL3 1x CLK 2x CLK 2x CLK 1M Gates LVCMOS LVTTL Processor Software Programmable GTL+ Old FPGA Old FPGA Inherently Programmable Backplane Logic Glue Logic PA Snowmass 9/99 26
27 Design Methodology Million-Gate Designs Variety of Design Flows Multiple HDLs In Use Global Design Teams This Requires Communication, Coordination and Integration! PA Snowmass 9/99 27
28 Modular Design Designer1 Module Designer3 Module Designer2 Module Design Reuse Autonomy between team members High Level Floorplanning Modular Place and Route Modular Time Specs With industry s best timing constraint language Modular Incremental Compile Extensive R&D investment Reduces Compile Time & Increases Performance PA Snowmass 9/99 28
29 Internet-Based Design WebFITTER, an Internet-based tool to evaluate CPLD designs Internet Team Design for team-based design over the Internet/Intranet Internet Reconfigurable Logic modify, upgrade, test, and repair FPGA-based systems by downloading new configurations via the Internet PA Snowmass 9/99 29
30 System on an FPGA VHDL Design Environment Verilog Design Environment CoreGen New Modules Designer #1 Designer #2 DSP FIFO IP Modules AllianceCore 133Mhz SDRAM Design Reuse CPU Gbit Ethernet PA Snowmass 9/99 30 LogiCore 66Mhz PCI 160 MHz I/O Performance 133 MHz Memory Performance 1 Million System Gates
31 Reconfigurable Logic Spectrum of Reconfiguration Once in a while Turn-on Application Tasks Continuous Field Upgrades Adaptive Products Multi-Personality Products Reconfigurable Computing Evolving Logic Cost-effective field upgrades New business model New types of products Mind-boggling opportunities in the long term Once-and-awhile PA Snowmass 9/99 31
32 Reconfigurable Instrument Multipurpose instrument can be reconfigured in milliseconds Single box for multiple applications Painless change,upgrade,or fix longer lifetime, lower cost Encourages experimentation faster progress Extends system lifetime lower cost PA Snowmass 9/99 32
33 Challenges PC-board interconnects and reflections Power consumption Radiation effects PA Snowmass 9/99 33
34 Moore Meets Einstein Trace Length in cm per 1/4 clock period Clock Frequency in MHz Year Speed Doubles Every 5 Years...But the speed of light never changes PA Snowmass 9/99 34
35 Transmission Lines Some traces must be treated as transmission lines to minimize ringing transmission line if round trip > transition time lumped-capacitance if round trip < transition time Signal delay on a PCB: 140 to 180 ps per inch ( 50 to 70 ps/cm) Lumped-capacitance trace length: 3 inches max for a 1-ns transition time (7.5 cm) 6 inches max for a 2-ns transition time (15 cm) PA Snowmass 9/99 35
36 Evolution (?) Max Clock Rate (MHz) Min IC Geometries (µ) # of IC Metal Layers PC Board Trace Width (µ) # of PC-Board Layers Every 5 years: System speed doubles, IC geometry shrinks 50% Every 7-8 years: PC-board minimum trace width shrinks 50% PA Snowmass 9/99 36
37 Power Consumption Power and heat are serious concerns All CMOS power consumption is dynamic proportional to capacitance = device utilization proportional to clock frequency proportional to Vcc 2 Virtex conserves power 2.5 V ( 1.8 V) supply, small geometries reduce capacitance built-in temperature-sensing diode for thermal management Airflow and heatsink achieve <10 / W PA Snowmass 9/99 37
38 Radiation Effects Xilinx XQR-series devices use 7-micron epitaxial layer to eliminate latch-up at LET up to 120 MeVcm 2 /mg Single-Event Upset (SEU) rates have been measured and reported FPGAs are being designed into aircraft and Low Earth Orbit Satellites (LEOS) See PA Snowmass 9/99 38
39 Living with Single-Event Upsets Read back configuration in <100 ms readback does not interfere with normal operation Error detection serial bit-comparison against original configuration abort and reconfigure whenever an error is detected Error correction use triple redundancy to sustain operation internal triple redundancy and fast partial reconfiguration in Virtex devices PA Snowmass 9/99 39
40 Conclusion SRAM-based FPGAs are the fastest-growing IC product category Technology equals that used for the most advanced microprocessors and memories Offers fast time-to-market and low design risk Density, speed, and cost challenge ASICs Reconfigurability is a unique advantage PA Snowmass 9/99 40
41 This is the Dawning of the Age of Programmable Logic PA Snowmass 9/99 41
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