TOTAL-IONIZING-DOSE RESPONSE OF 65 nm MOSFETS IRRADIATED TO ULTRA- HIGH DOSES. GIULIO BORGHELLO

Transcription

1 TOTAL-IONIZING-DOSE RESPONSE OF 65 nm MOSFETS IRRADIATED TO ULTRA- HIGH DOSES GIULIO BORGHELLO

2 introduction Presented at NSREC /11/2017 GIULIO BORGHELLO 2

3 introduction Presented at 2017 RADECS 14/11/2017 GIULIO BORGHELLO 3

4 introduction Typical test structure (65nm technology): Array of W (L=10um) Array of L (W=20um) Array of ELT (Enclosed Layout Transistors) Different Bias Charge pumping Only CORE transistors (no I/O) 14/11/2017 GIULIO BORGHELLO 4

5 introduction Total Ionizing Dose (TID) effects Single Event Effects (SEE) Displacement damage 14/11/2017 GIULIO BORGHELLO 5

6 introduction Overview on TID effects in CMOS technology. Radiation effects on 65nm technology. STI-related effects Spacers-related effects Low-dose-rate effects Qualification procedure. 14/11/2017 GIULIO BORGHELLO 6

7 TOTAL-DOSE EFFECTS: OVERVIEW 14/11/2017 GIULIO BORGHELLO 7

8 total-dose effects: overview High energy particles can create numerous electron-holes pairs. Holes can drift through the oxide toward the interface. H + play a key-role in creation of traps. nmos band diagram Schwank, James R., et al. IEEE Trans. Nucl. Sci (2008): [1] Rashkeev, S.N., et al. IEEE Trans. Nucl. Sci., 48.6 (2001): [1] nmos Oxide traps (fast built-up) + + Interface traps (slow built-up) - + The effects partially compensate each other pmos 14/11/2017 GIULIO BORGHELLO 8

9 total-dose effects: overview The sensitivity to TID decreases with the gate oxide thickness. 65 nm transistors, with gate oxide around 2 nm, should be very rad-hard. Saks, N. S., et al. IEEE Trans. on Nucl. Sci (1984): /11/2017 GIULIO BORGHELLO 9

10 total-dose effects: overview Huge performance degradation due to radiation effects in 65nm CMOS. I ON Faccio, F., et al. IEEE Trans. on Nucl. Sci (2015): /11/2017 GIULIO BORGHELLO 10

11 total-dose effects: overview Why such a large degradation? Several oxides present in CMOS technology (not only the gate oxide). Much thicker than the gate oxide (~100 nm). Lower quality with respect to gate oxide o rich in defects. process dependent. 14/11/2017 GIULIO BORGHELLO 11

12 total-dose effects: overview Shallow Trench Isolation (STI): useful to isolate adjacent devices. Spacers: Needed to create the Lightly Doped Source/Drain (LDD) extensions. 14/11/2017 GIULIO BORGHELLO 12

13 total-dose effects: overview Small W Large W STI-Related Effects Small L Large L Spacers-Related Effects 14/11/2017 GIULIO BORGHELLO 13

14 STI-RELATED EFFECTS 14/11/2017 GIULIO BORGHELLO 14

15 STI-related effects Before Irradiation After Irradiation Charge trapped in the oxide (faster) Large W Charge trapped at the interface, negative for nmos, positive for pmos (slower) Electric field Small W MOSFET top view MOSFET top view Radiation induced narrow channel effects (RINCE). 14/11/2017 GIULIO BORGHELLO 15

16 STI-related effects Irradiation nmos pmos Long channel! Marginal evolution Large degradation Annealing nmos pmos Slow evolution / slight recover. 14/11/2017 GIULIO BORGHELLO 16

17 STI-related effects Narrow channel nmos: Small influence of temperature. Long channel! Long channel! Narrow channel pmos: More rad-hard at low temperature. 14/11/2017 GIULIO BORGHELLO 17

18 STI-related effects Bias dependence: Irradiation o V gs > 0 lead to a heavier degradation at high dose. Annealing o nmos: Faster evolution if V gs > 0, but negligible recovery. o pmos: I ON slight recovery when V gs > 0. 14/11/2017 GIULIO BORGHELLO 18

19 STI-related effects Possible to avoid this effects whit hardness by design techniques like Enclose Layout Transistors (ELTs). The STI oxide does not face the channel. 14/11/2017 GIULIO BORGHELLO 19

20 STI-related effects STI-RELATED EFFECTS - RECAP Channel width-dependent behaviour Narrower transistors have larger radiation-induced degradation (RINCE). Radiation-induced current degradation o nmos small o pmos large Better performance at low temperature. Lower degradation with V gs = 0. Negligible evolution/small recovery during high temperature annealing. These problems can be addressed with RHBD approaches. 14/11/2017 GIULIO BORGHELLO 20

21 SPACERS-RELATED EFFECTS Spacer 14/11/2017 GIULIO BORGHELLO 21

22 spacers-related effects Two distinct radiation-induced mechanisms, strongly dependent on: Channel length (RISCE). Temperature. Applied bias. Transistor polarity. nmos pmos 25 o C 1 st and 2 nd effect 1 st effect 100 o C Slow evolution/small recovery 2 nd effect Easier to study. 14/11/2017 GIULIO BORGHELLO 22

23 spacers-related effects 1 st effect ELT: No STIrelated effects! 1 st Effect: Decrease of on-current during exposure. L-dependent (RISCE). pmos more damaged than nmos. Marginal V th shift. 14/11/2017 GIULIO BORGHELLO 23

24 spacers-related effects 1 st effect Much smaller R sd increase in nmos Smaller damage at low temperature! 14/11/2017 GIULIO BORGHELLO 24

25 spacers-related effects 2 nd effect 2 nd Effect: Large threshold voltage (V th ) shift. During or after irradiation, depending on: Channel length Temperature Bias Transistor polarity 14/11/2017 GIULIO BORGHELLO 25

26 spacers-related effects 2 nd effect Temperature plays a major role. Vgs=Vds=-1.2V Strongly bias-dependent effect. 14/11/2017 GIULIO BORGHELLO 26

27 spacers-related effects 2 nd effect When V gs = V ds = 1.2V, transistor gets asymmetric. REV = the role of source and drain is reversed. 14/11/2017 GIULIO BORGHELLO 27

28 spacers-related effects 2 nd effect Thanks to charge pumping measurements I cp we saw that defect density is larger above the source LDD extension (pmos). The I cp signal is larger when we pump the source more interface traps above the source LDD extension. 14/11/2017 GIULIO BORGHELLO 28

29 STI-related effects Annealing at different temperature after irradiation (100Mrad, pmos). Activation energy: 0.92 ev Drift of H + in SiO 2 ( ev) [2]. [2] Hofstein IEEE TED 14, 1967; McLean IEEE TNS 27, 1980; Saks IEEE TNS 35, /11/2017 GIULIO BORGHELLO 29

30 spacers-related effects 3-stage process: 1. Ionization in the spacers. 2. Transport of H + from the spacers to the channel region. 3. De-passivation of Si-H bonds.at the interface with the gate oxide. pmos have larger R sd increase than nmos. Larger damage for shorter length. 14/11/2017 GIULIO BORGHELLO 30

31 spacers-related effects 3-stage process: 1. Ionization in the spacers. 2. Transport of H + from the spacers to the channel region. 3. De-passivation of Si-H bonds.at the interface with the gate oxide. Coherent with the activation energy. Strong dependence on temperature and bias. 14/11/2017 GIULIO BORGHELLO 31

32 spacers-related effects 3-stage process: 1. Ionization in the spacers. 2. Transport of H + from the spacers to the channel region. 3. De-passivation of Si-H bonds.at the interface with the gate oxide. Large threshold voltage shift. F. Faccio, et. al, Influence of LDD spacers and h+ transport on the total-ionizing-dose response of 65 nm mosfets irradiated to ultra-high doses, Presented at the 2017 NSREC. 14/11/2017 GIULIO BORGHELLO 32

33 spacers-related effects We estimated the evolution of the 2 nd effect at low T. Solid lines: measured Dashed lines: estimated At -20 C it would take more than 400 years to halve the maximum drain current. 14/11/2017 GIULIO BORGHELLO 33

34 spacers-related effects nmos V th shift and asymmetry occur already at 25 C. Defects located at the drain side larger degradation in the reverse configuration. Recovery during high temperature annealing. In general less critical than pmos. 14/11/2017 GIULIO BORGHELLO 34

35 spacers-related effects Worst case: V gs = V ds = V dd Larger V th shift at high temperature. 14/11/2017 GIULIO BORGHELLO 35

36 spacers-related effects SPACERS-RELATED EFFECTS - RECAP Two main effects: o Increase in series resistance due to charge trapped in the spacer oxide or at its interface. o Protons (H + ) can move into the gate oxide provoking V th shift and asymmetry depending on channel length, temperature, bias and transistor polarity. The degradation is larger for Short channel lengths High temperatures V gs = V ds = V dd pmos Not easy to solve with layout techniques. 14/11/2017 GIULIO BORGHELLO 36

37 DIFFERENT 65nm MANUFACTURER COMPANY 14/11/2017 GIULIO BORGHELLO 37

38 STI-related effects RINCE and RISCE pmos less rad-hard then nmos Temperature-dependent large threshold voltage shift. 14/11/2017 GIULIO BORGHELLO 38

39 different 65nm manufacturer company Large radiation-induced increase of leakage current. nmos Leakage current 14/11/2017 GIULIO BORGHELLO 39

40 different 65nm manufacturer company UMC 65nm CMOS technology will be tested soon, in collaboration with Seville University. 14/11/2017 GIULIO BORGHELLO 40

41 LOW-DOSE-RATE EFFECTS 14/11/2017 GIULIO BORGHELLO 41

42 STI-related effects Larger current degradation at lower dose rates. Not time-dependent effect True enhanced LDR sensitivity. 14/11/2017 GIULIO BORGHELLO 42

43 low-dose-rate effects Johnston, A. H., et al. IEEE Trans. Nucl. Sci. vol (1995): Witczak, S. C., et al. IEEE Trans. on Nucl. Sci (1997): Larger damage at low-dose-rates. Smaller damage at low temperatures. Significant ELDRS is only observed in oxide layers with high defect densities irradiated at low electric fields. Fleetwood, Daniel M. IEEE Trans. on Nucl. Sci (2013): /11/2017 GIULIO BORGHELLO 43

44 low-dose-rate effects Similar effects also in 130nm CMOS technology. Courtesy of Szymon Kulis, CERN (EP-ESE-ME section). 14/11/2017 GIULIO BORGHELLO 44

45 low-dose-rate effects Temperature dependence? Dimension dependence? Bias dependence? STI or Spacers? 14/11/2017 GIULIO BORGHELLO 45

46 QUALIFICATION PROCEDURE 14/11/2017 GIULIO BORGHELLO 46

47 qualification procedure Typical qualification procedure (irradiation at room temperature + high-temperature annealing) could be excessively conservative. Fleetwood, D. M., and al. IEEE Trans. on Nucl. Sci 50.3 (2003): /11/2017 GIULIO BORGHELLO 47

48 qualification procedure 65nm mosfets are more rad-hard at low temperature during exposure. The temperature during exposure should be close to the real operating temperature. 14/11/2017 GIULIO BORGHELLO 48

49 qualification procedure Negligible evolution during annealing for narrow transistors. High temperature + bias accelerate the V th shift in short channel pmos. 1) No further annealing is needed. 2) Do not provide high temperature when the circuit is biased. 14/11/2017 GIULIO BORGHELLO 49

50 qualification procedure Both STI and spacers-related effects are, during irradiation, strongly bias-dependent. During irradiation tests the circuits must be biased. 14/11/2017 GIULIO BORGHELLO 50

51 qualification procedure DRAD chip T=100 C Several pmos permanently biased in the worst case. C T=-20 C T=60 C Casas, LM Jara, et al. Journal of Instrumentation (2017): C /11/2017 GIULIO BORGHELLO 51

52 qualification procedure The temperature during exposure should be close to the real operating temperature. During irradiation tests the circuits must be biased. No further annealing is needed. Valid only if in the application the circuit is never allowed to reach high temperatures under bias. 14/11/2017 GIULIO BORGHELLO 52

53 qualification procedure LDR effects could play an important role in the qualification procedures. Not feasible to perform true LDR tests. A more conservative approach would be needed. Higher temperature? How High? 14/11/2017 GIULIO BORGHELLO 53

54 THE END! CONCLUSIONS AND FUTURE ACTIVITIES We now have a reasonable picture of the physical mechanisms underlying the behaviour of irradiated 65nm CMOS technology. Performance degradation is mainly due to parasitic oxides. STI Spacers Thickness, poor quality and small electric fields could explain the temperature and dose-rate dependence. Intensive study about low-dose-rate effects in 65nm CMOS technology. A systematic study of 40nm and 28nm will be started. New test structures available soon. 14/11/2017 GIULIO BORGHELLO 54