VLSI Design I; A. Milenkovic 1

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1 PE/EE 427, PE 527 VLI esign I L8: Pass Transistor Logic epartment of Electrical and omputer Engineering University of labama in Huntsville leksandar Milenkovic ( www. ece.uah.edu/~milenka ) www. ece.uah.edu/~milenka/cpe527-3f [dapted from Rabaey s igital Integrated ircuits, 22, J. Rabaey et al. and Mary Jane Irwin ( www. cse. psu.edu/~mji ) ] ourse dministration Instructor: leksandar Milenkovic milenka@ece.uah.edu Office Hrs: MW 17:3-18:3, E217-L T: Fathima Tareen Office Hrs: Friday 11: 12: M, E246 URL: Text: igital Integrated ircuits, 2 nd Edition Rabaey et. al., 22 (October) Lab2: eptember 15 (posted), ue: October 1 Hw1: eptember 15 (posted), ue eptember 29 Project: efault project #1 posted! 9/2/23 VLI esign I;. Milenkovic 2 ombinational Logic ells (cont d) The OI family of cells with 3 index numbers or less = {OI, OI, O, O}; a,b,c={2,3} ell Type a1 a11 ab ab1 abc Total ells 21, , , 33, , 321, , 333, 332, 322 Number of Unique ells /2/23 VLI esign I;. Milenkovic 3 VLI esign I;. Milenkovic 1

2 OI221 Vdd E Z E 9/2/23 VLI esign I;. Milenkovic 4 tandard ell Layout Methodology Routing channel signals What logic function is this? 9/2/23 VLI esign I;. Milenkovic 5 OI21 Logic Graph j PUN =!( ( + )) i i j PN 9/2/23 VLI esign I;. Milenkovic 6 VLI esign I;. Milenkovic 2

3 Two tick Layouts of!( ( + )) uninterrupted diffusion strip 9/2/23 VLI esign I;. Milenkovic 7 onsistent Euler Path n uninterrupted diffusion strip is possible only if there exists a Euler path in the logic graph Euler path: a path through all nodes in the graph such that each edge is visited once and only once. i j For a single poly strip for every input signal, the Euler paths in the PUN and PN must be consistent (the same) 9/2/23 VLI esign I;. Milenkovic 8 onsistent Euler Path n uninterrupted diffusion strip is possible only if there exists a Euler path in the logic graph Euler path: a path through all nodes in the graph such that each edge is visited once and only once. i j For a single poly strip for every input signal, the Euler paths in the PUN and PN must be consistent (the same) 9/2/23 VLI esign I;. Milenkovic 9 VLI esign I;. Milenkovic 3

4 OI22 Logic Graph PUN =!((+) (+)) PN 9/2/23 VLI esign I;. Milenkovic 1 OI22 Layout ome functions have no consistent Euler path like x =!(a + bc + de) (but x =!(bc + a + de) does!) 9/2/23 VLI esign I;. Milenkovic 11 VT is ata-ependent M 3 M 4 3.5µ/.25 µ NMO.75 µ /.25 µ PMO 2,: -> 1 F= =1, : -> 1 weaker =1, :->1 M 2 PUN 1 V G2 = V V 1 int M 1 V G1 = V 1 2 The threshold voltage of M 2 is higher than M 1 due to the body effect (γ) V Tn1 = V Tn V Tn2 = V Tn + γ( ( 2φ F + V int ) - 2φ F ) since V of M 2 is not zero (when V = ) due to the presence of int 9/2/23 VLI esign I;. Milenkovic 12 VLI esign I;. Milenkovic 4

5 tatic MO Full dder ircuit in in! out in!um in in 9/2/23 VLI esign I;. Milenkovic 13! out =! in & (!!) (! &!) tatic MO Full dder ircuit!um= out & (!!! in ) (! &! &! in ) in in! out in!um in in out = in & ( ) ( & ) um=! out & ( in ) ( & & in ) 9/2/23 VLI esign I;. Milenkovic 14 NMO Transistors in eries/parallel Primary inputs drive both gate and source/drain terminals NMO switch closes when the gate input is high Y = Y if and Y = Y if or Remember NMO transistors pass a strong but a weak 1 9/2/23 VLI esign I;. Milenkovic 15 VLI esign I;. Milenkovic 5

6 PMO Transistors in eries/parallel Primary inputs drive both gate and source/drain terminals PMO switch closes when the gate input is low Y = Y if and = + Y = Y if or = Remember PMO transistors pass a strong 1 but a weak 9/2/23 VLI esign I;. Milenkovic 16 Pass Transistor (PT) Logic F = F = Gate is static a low-impedance path exists to both supply rails under all circumstances N transistors instead of 2N No static power consumption Ratioless idirectional (versus undirectional) 9/2/23 VLI esign I;. Milenkovic 17 VT of PT N Gate 1.5/.25.5/.25.5/.25.5/.25 F= V out, V 2 1 =, = 1 2 V in, V =, = == Pure PT logic is not regenerative- the signal gradually degrades after passing through a number of PTs (can fix with static MO inverter insertion) 9/2/23 VLI esign I;. Milenkovic 18 VLI esign I;. Milenkovic 6

7 ifferential PT Logic (PL) PT Network F F Inverse PT Network F F F= F=+ F= N/NN F= OR/NOR F=+ OR/NOR F= 9/2/23 VLI esign I;. Milenkovic 19 PL Properties ifferential so complementary data inputs and outputs are always available (so don t need extra inverters) till static, since the output defining nodes are always tied to or through a low resistance path esign is modular; all gates use the same topology, only the inputs are permuted. imple OR makes it attractive for structures like adders Fast (assuming number of transistors in series is small) dditional routing overhead for complementary signals till have static power dissipation problems 9/2/23 VLI esign I;. Milenkovic 2 PL Full dder in in!um um in in in in! out out 9/2/23 VLI esign I;. Milenkovic 21 VLI esign I;. Milenkovic 7

8 PL Full dder in in!um um in in in in! out out 9/2/23 VLI esign I;. Milenkovic 22 NMO Only PT riving an Inverter In = V V x = G = -V Tn M 1 M 2 V x does not pull up to, but V Tn Threshold voltage drop causes static power consumption (M 2 may be weakly conducting forming a path from to ) Notice V Tn increases of pass transistor due to body effect (V ) 9/2/23 VLI esign I;. Milenkovic 23 Voltage wing of PT riving an Inverter In = 1.5/.25 x Out.5/.25.5/.25 ody effect large V at x - when pulling high ( is tied to and charged up close to ) o the voltage drop is even worse V x = - (V Tn + γ( ( 2φ f + V x ) - 2φ f )) Voltage, V Out In x = 1.8V Time, ns 9/2/23 VLI esign I;. Milenkovic 24 VLI esign I;. Milenkovic 8

9 ascaded NMO Only PTs = = G M 1 = x = - V Tn1 G y M 2 = Out = = x y M 1 M 2 Out wing on y = - V Tn1 - V Tn2 wing on y = - V Tn1 Pass transistor gates should never be cascaded as on the left Logic on the right suffers from static power dissipation and reduced noise margins 9/2/23 VLI esign I;. Milenkovic 25 olution 1: Level Restorer Level Restorer on =1 M 2 Out= = M n M r off x= 1 M 1 Out =1 Full swing on x (due to Level Restorer) so no static power consumption by inverter No static backward current path through Level Restorer and PT since Restorer is only active when is high For correct operation M r must be sized correctly (ratioed) 9/2/23 VLI esign I;. Milenkovic 26 Transient Level Restorer ircuit Response 3 W/L 2 =1.5/.25 W/L n =.5/.25 W/L 1 =.5/.25 Voltage, V 2 1 W/L r =1.75/.25 W/L r =1.5/.25 node x never goes below V M of inverter so output never switches W/L r =1.25/.25 W/L r =1./ Time, ps Restorer has speed and power impacts: increases the capacitance at x, slowing down the gate; increases t r (but decreases t f ) 9/2/23 VLI esign I;. Milenkovic 27 VLI esign I;. Milenkovic 9

10 olution 2: Multiple V T Transistors Technology solution: Use (near) zero V T devices for the NMO PTs to eliminate most of the threshold drop (body effect still in force preventing full swing to ) low V T transistors In 2 = V = 2.5V on Out In 1 = 2.5V off but leaking = V sneak path Impacts static power consumption due to subthreshold currents flowing through the PTs (even if V G is below V T ) 9/2/23 VLI esign I;. Milenkovic 28 olution 3: Transmission Gates (TGs ) Most widely used solution = = = = = = Full swing bidirectional switch controlled by the gate signal, = if = 1 9/2/23 VLI esign I;. Milenkovic 29 olution 3: Transmission Gates (TGs ) Most widely used solution = = = = = = Full swing bidirectional switch controlled by the gate signal, = if = 1 9/2/23 VLI esign I;. Milenkovic 3 VLI esign I;. Milenkovic 1

11 Resistance of TG Resistance, kω R p W/L p =.5/.25 V R n R p 2.5V V out R n 2.5V R eq W/L n =.5/ V out, V 9/2/23 VLI esign I;. Milenkovic 31 TG Multiplexer F In 2 F In 1 F =!(In 1 + In 2 ) In 1 In 2 9/2/23 VLI esign I;. Milenkovic 32 Transmission Gate OR 9/2/23 VLI esign I;. Milenkovic 33 VLI esign I;. Milenkovic 11

12 Transmission Gate OR weak if! 1 off on off on!! weak 1 if an inverter 9/2/23 VLI esign I;. Milenkovic 34 TG Full dder in um out 9/2/23 VLI esign I;. Milenkovic 35 ifferential TG Logic (PL) F= F= F= F= N/NN OR/NOR 9/2/23 VLI esign I;. Milenkovic 36 VLI esign I;. Milenkovic 12