Outline Single Cycle Processor Design Multi cycle Processor. Pipelined Processor: Hazards and Removal. Instruction Pipeline. Time
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1 3/8/5 Pipelined Processor: Hazards and its Removal A. Sahu CSE, T Guwahati Please be updated with Outline Single Cycle Processor esign Multi cycle Processor Merging M and M, Removing Adder and Adder Synchronized : ntroducing Mux and Register Pipelined Processor (ata Path) Pipeline : ntroduction and Performance, Cost Pipelined Processor: Hazards and Removal ata Hazards : Bypass/forward Path Control Hazards : Branch Prediction NS NS nstruction Pipeline Time or Cycle Clock T nstruction Pipeline Time To Execute N nstruction : Total Time= T*N*5 No Pipeline NS 3 NS 4 Pipeline NS 5 All the Stages work in parallel, No resource can be shared by stages Performance: uction per Cycle 3 Total Time= T*(N4) 4 Superscalar Pipeline: Pentium Single Pipeline Pipeline Pipeline Pipeline3 Fetch 3 uctions ecode 3 uctions Execute 3 nstructions 5 ifficulties in Pipeline
2 3/8/5 Hazards in Pipelining Resource conflicts => Structural hazards use of same resource in different stages ata dependencies => ata hazards RAW (read after write) WAR (write after read) WAW (write after write) Procedural dependencies => Control hazards conditional and unconditional branches, calls/returns Structural Hazards Structural Hazards Caused by Resource Conflicts Use of a hardware resource in more than one cycle A B A C A B A C A B A C Hazards & Handle Resource Hazards : We don t allow this to happen Hardware ependent ifferent sequences of resource usage by different uctions Non pipelined multi cycle resources A B C A C B F X X F X X ata Hazards : ata ependency Control Hazards: JMP, Call, RTN, BEQ, BNZ,.. Program ependent: Hardware designer don t have any control nstruction Pipeline: ata hazards ata Hazards LW R, LW R, 4 A R3, R, R SW R3, 8 Clock F F F Time F Result of is used by 3: Complete then start 3 Result of 3 is used by 4: Complete 3 then start 4
3 3/8/5 previous current ata Hazards read/write read/write s due to data hazards M M M M M M M : lw $t,... add $s,$t,.. delay = 3 Fun: not considering R in nd Half of cycle and W in st half of Cycle ata hazards: Handling with data forwarding M M : lw $t,... add $s,$t,.. ata hazards: Handling with data forwarding M M : lw $t,... add $s,$t,.. M M M M M M M Create an extra Forward Path from ory to Create an extra Forward Path from ory to Fun: not considering R in nd Half of cycle and W in st half of Cycle Fun: not considering R in nd Half of cycle and W in st half of Cycle s due to data hazards uction view M M M M M : lw $t,... add $s,$t,.. M M M HA..HA.. : Considering R in nd Half of cycle and W in st half of Cycle previous current previous current Handling ata Hazards R W ata Forwarding W nsert many non dependent uctions in between both R nstruction Reordering 3
4 3/8/5 Control Hazards s due to control hazards We will get result here M M M : beq...,l... L: add... M L M M We need to wait till Result of comparison Examples Suppose a processor with S stages pipeline When we encounter a branch uction, whole pipeline need to be flushed, till execution (finishing) of the branch uction t will take S cycle Probability of branch is b Performance of Program with N uctions Execution time = N ( Branch Prob * Branch Penalty ) = N( b (S ) ) Cycles branch next inline target General Branch nstruction target addr gen delay = delay = 5 cond eval the order of cond eval and target addr gen may be different cond eval may be done in previous uction branch next inline target General Branch nstruction cond eval delay = delay = 5 target addr gen the order of cond eval and target addr gen may be different cond eval may be done in previous uction Remember BEQ nstruction : BEQ $S $S 6bitLabel if (S==S) PC= (PC4) SinX3(6BitLabel<<); else PC = PC4; Address gen : SinX3(6BitLabel<<); Condition eval : S==S F /R M S==S SinX3(Label<<); SinX3(Label<<); S==S 4
5 3/8/5 Handling ata Hazards Handling hazards ata hazards detect uctions with data dependence introduce nop uctions (bubbles) in the pipeline more complex: data forwarding Control hazards detect branch uctions flush inline uctions if branching occurs more complex: branch prediction Pipeline ata Hazards s due to data hazards Control to introduce stall cycles etecting data hazard conditions ata forwarding paths ata forwarding control s with data forwarding s due to data hazards uction view M M M M M : lw $t,... add $s,$t,.. M M M etecting data hazard Condition to be checked: nstruction in stage reads from a register in which uction in stage or M stage is going to write /.RW and (F/.rs=/.rd or F/.rt=/.rd) /M.RW and (F/.rs=/M.rd or F/.rt=/M.rd) We need to ensure that uction in actually reads rs and/or rt (not taken care here) Note: rd is the destination address after multiplexing ata forwarding path P M M M M : add $t,... add $s,$t, to 5
6 3/8/5 ata forwarding path P M M : lw $t,... add $s,$t,.. ata forwarding path P3 M M : add $t,... sw $t,.. M M M M M M M to M to M by passing ata forwarding path P4 M M M M M : lw $t,... sw $t,.. M to M by passing ata forwarding path list P from out (/M) to in/ P from M/ out (M/) to in/ P3/P4 from M/ out (M/) to M in Actual forwarding paths / / / fwda fwdb fwdc ad rd M wd Handling Control Hazards 6
7 3/8/5 Handling Control Hazards Branch Elimination Predicate uction Branch Speed up Early CC, elayed branch Branch Prediction Fixed, Static, ynamic Branch target capture BTB, BTAC, BTC Branch Elimination Branch Elimination Branch Elimination: SLT C S T OP BC CC = Z, A R3, R, R OP F Use conditional uctions (predicated execution) C : S OP A R3, R, R, NZ OP Set on less then (SLT) SLT R R R3 Meaning if (R < R ) R3= Suppose if you don t have this NS CMP R R JNZ Label MOV R3 Label: Branch Speed up 7
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