Data Hazards. Result does not feed back around in time for next operation Pipelining has changed behavior of system. Comb. logic A. R e g.
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1 ata Hazards Comb. logic A R e g Comb. logic B R e g Comb. logic C R e g OP1 A B C OP2 A B C OP3 A B C OP4 A B C Time Clock Result does not feed back around in time for next operation Pipelining has changed behavior of system
2 _icode, _valm _vale, _valm, _dste, _dstm Pipeline Stages Fetch Select current Read instruction Compute incremented ecode Read program registers Execute Operate ALU Memory Read or write data memory rite Back Update register file Memory Execute ecode Fetch M_icode, M_Bch, M_valA M E icode, ifun, ra, rb, valc F Instruction memory Addr, ata Bch d_srca, d_srcb valm CC alua, alub ata memory valp vale ALU vala, valb increment f_ A B M Register file valp E rite back pred
3 Predicting the icode ifun ra rb valc valp Predict M_icode M_Bch M_valA _icode _valm Instr valid Need valc Need regids increment Split Align Byte 0 Bytes 1-5 Instruction memory Select F pred Start fetch of new instruction after current one has completed fetch stage Not enough time to reliably determine next instruction Guess which instruction will follow Recover if prediction was incorrect
4 Our Prediction Strategy Instructions that on t Transfer Control Predict next to be valp Always reliable Call and Unconditional Jumps Predict next to be valc (destination) Always reliable Conditional Jumps Predict next to be valc (destination) Only correct if branch is taken Typically right 60% of time Return Instruction on t try to predict
5 Recovering from icode ifun ra rb valc valp M_icode M_Bch M_valA _icode _valm Misprediction Instr valid Need valc Need regids increment Predict Split Align Byte 0 Bytes 1-5 Instruction memory Select F pred Mispredicted Jump ill see branch flag once instruction reaches memory stage Can get fall-through from vala Return Instruction ill get return when ret reaches write-back stage
6 Pipeline emonstration irmovl $1,%eax #I1 F E M irmovl $2,%ecx #I2 F E M irmovl $3,%edx #I3 F E M irmovl $4,%ebx #I4 F E M halt #I5 F E M Cycle 5 I1 M I2 E I3 #demo-basic.ys I4 F I5
7 ata ependencies: 3 Nop s # demo-h3.ys 0x000: irmovl $10,% edx F E M 0x006: irmovl $3,% eax F E M 0x00c: nop F E M 0x00d: nop F E M 0x00e: nop F E M 0x00f: addl % edx,% eax F E M 0x011: halt F E M Cycle 6 R[ % eax ] f 3 Cycle 7 vala f R[ % edx ] = 10 valb f R[ % eax ] = 3
8 ata ependencies: 2 Nop s # demo-h2.ys 0x000: irmovl $10,% edx F E M 0x006: irmovl $3,% eax F E M 0x00c: nop F E M 0x00d: nop F E M 0x00e: addl % edx,% eax F E M 0x010: halt F E M 10 Cycle 6 R[ % eax ] f 3 vala f R[ % edx ] = 10 valb f R[ % eax ] = 0 Error
9 ata ependencies: 1 Nop # demo-h1.ys x000: irmovl $10,% edx F E M 0x006: irmovl $3,% eax F E M 0x00c: nop F E M 0x00d: addl % edx,% eax F E M 0x00f: halt F E M Cycle 5 R[ % edx ] f 10 M M_ vale = 3 M_ dste = % eax vala f R[ % edx ] = 0 valb f R[ % eax ] = 0 Error
10 ata ependencies: No Nop # demo-h0.ys x000: irmovl $10,% edx F E M 0x006: irmovl $3,% eax F E M 0x00c: addl % edx,% eax F E M 0x00e: halt F E M Cycle 4 M M_ vale = 10 M_ dste = % edx E e_ vale f = 3 E_ dste = % eax vala f R[ % edx ] = 0 valb f R[ % eax ] = 0 Error
11 Return Example demo-ret.ys 0x000: irmovl Stack,%esp # Intialize stack pointer 0x006: nop # Avoid hazard on %esp 0x007: nop 0x008: nop 0x009: call p # Procedure call 0x00e: irmovl $5,%esi # Return point 0x014: halt 0x020:.pos 0x20 0x020: p: nop # procedure 0x021: nop 0x022: nop 0x023: ret 0x024: irmovl $1,%eax # Should not be executed 0x02a: irmovl $2,%ecx # Should not be executed 0x030: irmovl $3,%edx # Should not be executed 0x036: irmovl $4,%ebx # Should not be executed 0x100:.pos 0x100 0x100: Stack: # Stack: Stack pointer Require lots of nops to avoid data hazards
12 Stalling for ata ependencies # demo-h2.ys x000: irmovl $10,%edx F E M 0x006: irmovl $3,%eax F E M 0x00c: nop F E M 0x00d: nop F E M bubble E M 0x00e: addl %edx,%eax F E M 0x010: halt F F E M If instruction follows too closely after one that writes register, slow it down Hold instruction in decode ynamically inject nop into execute stage
13 etecting Stall Condition # demo-h2.ys x000: irmovl $10,%edx F E M 0x006: irmovl $3,%eax F E M 0x00c: nop F E M 0x00d: nop F E M bubble E M 0x00e: addl %edx,%eax F E M 0x010: halt F F E M Cycle 6 _dste = %eax _vale = 3 srca = %edx srcb = %eax
14 Stalling X3 # demo-h0.ys x000: irmovl $10,%edx F E M 0x006: irmovl $3,%eax F E M bubble E M bubble E M bubble E M 0x00c: addl %edx,%eax F E M 0x00e: halt F F F F E M Cycle 6 Cycle 4 E E_dstE = %eax srca = %edx srcb = %eax Cycle 5 M M_dstE = %eax srca = %edx srcb = %eax _dste = %eax srca = %edx srcb = %eax
15 hat Happens hen Stalling? # demo-h0.ys 0x000: irmovl $10,%edx 0x006: irmovl $3,%eax 0x00c: addl %edx,%eax 0x00e: halt rite Back Memory Execute ecode Fetch Cycle x000: 0x006: irmovl bubble $10,%edx $3,%eax 0x000: 0x006: irmovl bubble $10,%edx $3,%eax 0x006: 0x00c: irmovl bubble addl %edx,%eax $3,%eax 0x00c: 0x00e: addl halt %edx,%eax 0x00e: halt Stalling instruction held back in decode stage Following instruction stays in fetch stage Bubbles injected into execute stage Like dynamically generated nop s Move through later stages
16 Avoiding Load/Use Hazard # demo-luh.ys x000: irmovl $128,%edx Stall using instruction for one cycle Can then pick up loaded value by forwarding from memory stage F E M 0x006: irmovl $3,%ecx F E M 0x00c: rmmovl %ecx, 0(%edx) F E M 0x012: irmovl $10,%ebx F E M 0x018: mrmovl 0(%edx),%eax # Load %eax F E M bubble E M 0x01e: addl %ebx,%eax # Use %eax F E M 0x020: halt F F E M Cycle 8 _dste = %ebx _vale = 10 M M_dstM = %eax m_valm f M[128] = 3 vala f _vale = 10 valb f m_valm = 3
17 Mem. control ata memory memory etecting Load/Use Hazard Memory M_Bch write M_valE Addr data in M_valA M icode Bch vale vala dste dstm e_bch CC ALU ALU fun. e_vale Execute ALU A ALU B E icode ifun valc vala valb dste dstm srca srcb dste d_srca d_srcb dstm srca srcb Sel+Fwd A Fwd B ecode A B M Register file E _valm _vale icode ifun ra rb valc valp Condition Fetch Load/Use Hazard F Instruction memory f_ Trigger increment Predict M_valA Select E_icode in { IMRMOVL, _valm IPOPL } && E_dstM in { d_srca, d_srcb } pred
18 Control for Load/Use Hazard # demo - luh. ys x000: irmovl $128,% edx F E M 0x006: irmovl $3,% ecx F E M 0x00c: rmmovl % ecx, 0(% edx ) F E M 0x012: irmovl $10,% ebx F E M 0x018: mrmovl 0(% edx ),% eax # Load % eax F E M bubble E M 0x01e: addl % ebx,% eax # Use % eax F E M 0x020: halt F F E M Stall instructions in fetch and decode stages Inject bubble into execute stage Condition F E M Load/Use Hazard stall stall bubble normal normal
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