Lecture 7: Pipelined Implementation. James C. Hoe Department of ECE Carnegie Mellon University

Transcription

1 8 447 Lectre 7: Pipelined Implementation James C. Hoe Department of ECE Carnegie ellon University S8 L7 S, James C. Hoe, CU/ECE/CALC, 28

2 Yor goal today S8 L7 S2, James C. Hoe, CU/ECE/CALC, 28 Hosekeeping getting started on pipelined implementations Notices Lab, Part B, de tomorrow HW,past de Handot #5: Lab 2 Handot #6: HW 2 Handot #7: HW soltions **Office Hors: ~2 and F :3~2:3** ings P&H Ch 4

3 Doing landry more qickly: in theory Time Task order A B C D 6 P A. place one dirty load of clothes in washer 2. when washer is finished, place wet clothes in dryer 3. when dryer is finished, yo fold dried clothes 4. when folding is finished, ask friend to pt clothes away steps to do a load are seqentially dependent no dependence between different loads different steps do not share resorces S8 L7 S3, James C. Hoe, CU/ECE/CALC, 28 [P&H CO&D, COPYRIGHT 24 Elsevier. ALL RIGHTS RESERVED.]

4 Doing landry more qickly: in theory Time Task order A B C D 6 P A Time 6 P A Task order S8 L7 S4, James C. Hoe, CU/ECE/CALC, 28 A B C D 4 loads of landry in parallel no additional resorces (all resorces always bsy!) throghpt increased by 4 latency per load is the same Based on original figre from [P&H CO&D, COPYRIGHT 24 Elsevier. ALL RIGHTS RESERVED.]

5 Doing landry more qickly: in practice Time Task order A B C D 6 P A Time 6 P A Task order A B C D the slowest step decides throghpt S8 L7 S5, James C. Hoe, CU/ECE/CALC, 28 Based on original figre from [P&H CO&D, COPYRIGHT 24 Elsevier. ALL RIGHTS RESERVED.]

6 Doing landry more qickly: in practice Time Task order A B C D 6 P A Time 6 P A Task order S8 L7 S6, James C. Hoe, CU/ECE/CALC, 28 A B C D A B A B Throghpt restored (2 loads per hor) sing 2 dryers Based on original figre from [P&H CO&D, COPYRIGHT 24 Elsevier. ALL RIGHTS RESERVED.]

7 (Ideal) HW Pipelining combinational logic T psec Rate=~(/T) T/2 psec T/2 psec Rate=~(2/T) T/3 psec T/3 psec T/3 psec Rate=~(3/T) S8 L7 S7, James C. Hoe, CU/ECE/CALC, 28 Notice: evenly divisible; no feedback wires

8 Performance odel Nonpipelined version with delay T Rate = /(T+S) where S = latch delay T psec k stage pipelined version Rate k stage = / (T/k +S ) Rate ma = / ( gate delay + S ) T/k psec T/k psec S8 L7 S8, James C. Hoe, CU/ECE/CALC, 28 per task latency became longer: T+kS

9 Cost odel Nonpipelined version with combinational cost G Cost = G+L where L = latch cost G gates k stage pipelined version Cost k stage = G + Lk G/k G/K S8 L7 S9, James C. Hoe, CU/ECE/CALC, 28

10 Reality of Pipelining.... [25 ] Shift Jmp address [3 ] left PCSrc =Jmp 4 PC+4 [3 28] [3 26] Control RegDst Jmp Branch em emtoreg Op em Src Reg Shift left 2 reslt PCSrc 2 =Br Taken PC address [3 ] [25 2] [2 6] [5 ] register register 2 Registers 2 register Zero reslt bcond ress [5 ] 6 Sign 32 etend control [5 ] Based on original figre from [P&H CO&D, COPYRIGHT 24 Elsevier. ALL RIGHTS RESERVED.] S8 L7 S, James C. Hoe, CU/ECE/CALC, 28 T Rate=~(/T)

11 8 447 S8 L7 S, James C. Hoe, CU/ECE/CALC, 28 Pipeline Idealism otivation: Increase throghpt withot adding hardware cost Repetition of identical tasks same task repeated for many different inpts Repetition of independent tasks no ordering dependencies between repeated tasks Uniformly partitionable sboperations arbitrary nmber and placement of bondaries Good eamples: atomobile assembly line, doing landry, bt instrction eection???

12 RISC Processing 5 generic steps instrction fetch instrction decode and operand fetch /eecte access write back IF Register # PC ress Registers Register # ID Register # EX WB ress E S8 L7 S2, James C. Hoe, CU/ECE/CALC, 28 Based on original figre from [P&H CO&D, COPYRIGHT 24 Elsevier. ALL RIGHTS RESERVED.]

13 Coalescing and Eternal Fragmentation steps IF ID EX E WB R type I type LW SW B/JALR JAL IF Register # PC ress Registers Register # ID Register # EX WB ress E S8 L7 S3, James C. Hoe, CU/ECE/CALC, 28 Based on original figre from [P&H CO&D, COPYRIGHT 24 Elsevier. ALL RIGHTS RESERVED.]

14 Dividing into Stages 2ps ps 2ps 2ps ps IF: fetch ID: decode/ register file read EX: Eecte/ address calclation E: emory access WB: back ignore for today 4 Shift left 2 reslt PC ress register register 2 Registers 2 register Zero reslt ress RF write 6 Sign etend 32 Is this the correct partitioning? Why not 4 or 6 stages? Why not different bondaries S8 L7 S4, James C. Hoe, CU/ECE/CALC, 28 Based on original figre from [P&H CO&D, COPYRIGHT 24 Elsevier. ALL RIGHTS RESERVED.]

15 Internal and Eternal Fragmentation Program eection order Time (in instrctions) lw $, ($) fetch Reg access Reg lw $2, 2($) 8ps 8 ns fetch Reg access Reg lw $3, 3($) Program eection Time order (in instrctions) lw $, ($) fetch 8 8ps ns Reg access Reg fetch 8ps 8 ns... lw $2, 2($) 2ps 2 ns fetch Reg access Reg lw $3, 3($) 2ps 2 ns fetch Reg access Reg 5 stage speedp is only 4 Not all resorces % tilized S8 L7 S5, James C. Hoe, CU/ECE/CALC, 28 2ps 2 ns 2ps 2 ns 22ps ns 2ps 2 ns 2ps 2 ns Based on original figre from [P&H CO&D, COPYRIGHT 24 Elsevier. ALL RIGHTS RESERVED.]

16 Pipeline Registers IF: fetch ID: decode/ register file read EX: Eecte/ address calclation E: emory access WB: back No resorce is sed by more than stage! IF/ID ID/EX EX/E E/WB 4 4 PC D +4 PC E +4 reslt reslt npc Shift Shift left left 2 2 PC F PC PC ress ress IR D register register register 2 2 Registers 2 2 register register Sign Sign etend etend A E B E Imm E Zero Zero reslt reslt Aot B ress ress DR W Aot W Based on original figre from [P&H CO&D, COPYRIGHT 24 Elsevier. ALL RIGHTS RESERVED.] S8 L7 S6, James C. Hoe, CU/ECE/CALC, 28 T/k ps T T/k ps

17 Pipelined Operation lw fetch lw decode lw Eection lw emory lw back IF/ID ID/EX EX/E EX/E E/WB 4 Shift left 2 reslt PC PC ress register register 2 Registers 2 register 6 6 Sign etend Zero reslt ress S8 L7 S7, James C. Hoe, CU/ECE/CALC, 28 Based on original figre from [P&H CO&D, COPYRIGHT 24 Elsevier. ALL RIGHTS RESERVED.]

18 Pipelined Operation sb lw $, $, 2($) $2, $3 fetch sb lw $, $, 2($) $2, $3 decode lw $, 2($) Eection sb $, $2, $3 Eection sb lw $, $, 2($) $2, $3 emory sb lw $, $, 2($) $2, $3 back IF/ID ID/EX EX/E E/WB 4 Shift left 2 reslt PC ress register register 2 Registers 2 register 6 Sign etend 32 Zero reslt ress Clock Clock Clock S8 L7 S8, James C. Hoe, CU/ECE/CALC, 28 Based on original figre from [P&H CO&D, COPYRIGHT 24 Elsevier. ALL RIGHTS RESERVED.]

19 Illstrating Pipeline Operation: Resorce View t t t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t IF I I I 2 I 3 I 4 I 5 I 6 I 7 I 8 I 9 I ID I I I 2 I 3 I 4 I 5 I 6 I 7 I 8 I 9 EX I I I 2 I 3 I 4 I 5 I 6 I 7 I 8 E I I I 2 I 3 I 4 I 5 I 6 I 7 WB I I I 2 I 3 I 4 I 5 I S8 L7 S9, James C. Hoe, CU/ECE/CALC, 28

20 Illstrating Pipeline Operation: Operation View t t t 2 t 3 t 4 t 5 Inst Inst Inst 2 Inst 3 Inst 4 IF ID IF EX ID IF E EX ID IF WB E EX ID IF WB E EX ID IF WB E EX ID IF WB E EX ID IF S8 L7 S2, James C. Hoe, CU/ECE/CALC, 28

21 Eample: after Hazard addi ra r addi r ra addi r ra addi r ra addi r ra addi r ra t t t 2 t 3 t 4 t 5 IF ID EX E WB IF ID EX E WB IF ID EX E IF ID EX IF? ID IF S8 L7 S2, James C. Hoe, CU/ECE/CALC, 28

22 Eample: Pipeline Stalls t t t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t IF I I I 2 I 3 I 4 I 4 I 4 I 4 I 5 I 6 I 7 ID I I I 2 I 3 I 3 I 3 I 3 I 4 I 5 I 6 EX I I I 2 I 3 I 4 I 5 E I I I 2 I 3 I 4 WB I I I 2 I S8 L7 S22, James C. Hoe, CU/ECE/CALC, 28 I 2 =addi ra, r, ; I 3 =addi r, ra, ;

23 Control Points PCSrc IF/ID ID/EX EX/E E/WB 4 Reg Shift left 2 reslt Branch PC ress register register 2 Registers 2 register [5 ] 6 Sign 32 etend Src 6 control Zero reslt ress em em emtoreg Based on original figre from [P&H CO&D, COPYRIGHT 24 Elsevier. ALL RIGHTS RESERVED.] [2 6] [5 ] RegDst Op S8 L7 S23, James C. Hoe, CU/ECE/CALC, 28 Identical set of control points as the single cycle path!!

24 Seqential Control: Special Case For a given instrction same control settings as single cycle, bt control signals reqired at different cycles, depending on stage decode once sing the same logic as single cycle and bffer control signals ntil consmed WB Control WB EX WB S8 L7 S24, James C. Hoe, CU/ECE/CALC, 28 IF/ID ID/EX EX/E E/WB

25 Pipelined Control PCSrc Control ID/EX WB EX/E WB E/WB IF/ID EX WB PC 4 ress Reg register register 2 Registers 2 register Shift left 2 reslt Src Zero reslt Branch em ress emtoreg [5 ] 6 Sign 32 etend 6 control em Based on original figre from [P&H CO&D, COPYRIGHT 24 Elsevier. ALL RIGHTS RESERVED.] [2 6] [5 ] S8 L7 S25, James C. Hoe, CU/ECE/CALC, 28 RegDst Op This is all there is to it (withot hazards)!!

26 Pipeline Reality Not identical tasks coalescing instrction types into one mltifnction pipe eternal fragmentation (some idle stages) Not niform sboperations grop or sb divide steps into stages to minimize variance internal fragmentation (some too fast stages ) Not independent tasks dependency detection and resoltion net lectre(s) Even more messy if not RISC S8 L7 S26, James C. Hoe, CU/ECE/CALC, 28

27 dependence r 3 r op r r 5 r 3 op r 4 Anti dependence r 3 r op r r r 4 op r 5 Dependence after (RAW) after (WAR) Otpt dependence r 3 r op r 2 after (WAW).... r 3 r 6 op r 7 Don t forget instrctions S8 L7 S27, James C. Hoe, CU/ECE/CALC, 28

28 C Code Control Dependence Control Flow Graph code A Assembly Code (linearized) code A { code A } if X==Y then { code B } else { code C } { code D } Tre if X==Y False code B code C code D if X==Y goto code C goto code B code D Does B or C come after A? S8 L7 S28, James C. Hoe, CU/ECE/CALC, 28