CS650 Computer Architecture. Lecture 5-1 Branch Hazards

Transcription

1 CS65 Computer Architecture Lecture 5- Branch Hazards Andrew Sohn Computer Science Department New Jersey Institute of Technology Lecture 5-: Branch Hazards 5--/6 /5/24 A. Sohn Simple 5-Stage Computer 4 add add PC ion ory instruction reg reg2 isters reg 2 sign extend ory Lecture 5-: Branch Hazards 5--2/6 /5/24 A. Sohn

2 Branch Hazards: What To Do? beq r,r2,offset sub r4,r,r5 and r6,r,r7 or r8,r,r9 computation next/branch Lecture 5-: Branch Hazards 5--3/6 /5/24 A. Sohn Clock Simple Stall the Pipe for Every Branch beq r,r2,offset sub r4,r,r5 Stall Stall and r6,r,r7 for each branch stall the pipe whether taken or not. or r8,r,r9 computation branch/next Clock Lecture 5-: Branch Hazards 5--4/6 /5/24 A. Sohn

3 Cost of Stalling for Branch Lose three cycles for every branch? How about Consider this loop: for (i=;i<n;i++) { a[i]=b[i]+c[i]; } addi r5,r,#4n loop: load r2,offset-b(r5) load r3,offset-c(r5) add r,r2,r3 store offset-a(r5),r subi r5,r5,#4 bne r5,loop ;initialize the pointer to 4n ;r2=b[n-] ;r3=c[n-] ;a=b+c ;decrement the counter by 4 bytes ;branch if not done A lot of loss for this simple loop. How many clock loss? Why? And solutions? Lecture 5-: Branch Hazards 5--5/6 /5/24 A. Sohn Modified Pipeline 4 add add PC ion ory instruction reg reg2 isters reg 2 sign extend ory Lecture 5-: Branch Hazards 5--6/6 /5/24 A. Sohn

4 Stall Even If Branch Not Taken beq r,r2,offset sub r4,r,r5 Stall and r6,r,r7 or r8,r,r9 computation next/branch Clock Lecture 5-: Branch Hazards 5--7/6 /5/24 A. Sohn Predict-Not-Taken on the Modified Pipeline 4 add add PC ion ory instruction reg reg2 isters reg 2 sign extend ory Lecture 5-: Branch Hazards 5--8/6 /5/24 A. Sohn

5 Predict-Not-Taken:Branch Not-Taken beq r,r2,offset sub r4,r,r5 and r6,r,r7 or r8,r,r9 computation next Clock Lecture 5-: Branch Hazards 5--9/6 /5/24 A. Sohn Predict-Not-Taken: Branch Taken beq r,r2,offset sub r4,r,r5 target target + target + 2 computation branch Clock Lecture 5-: Branch Hazards 5--/6 /5/24 A. Sohn

6 Delayed Branch Still a clock loss. Any further improvement? Called Delayed Branch Fill the stalled/lost cycle with something productive regardless of the branch testing result. What is that someting productive? - has to be computed whether the branch is taken or not - should not interfere with other instructions - must produce correct results How do we find that something? Lecture 5-: Branch Hazards 5--/6 /5/24 A. Sohn Delayed Branch load r6, (r7) add r, r2, r3 nop or r9,r,r mul r6,r7,r8 before load r6, (r7) add r,r2,r3 or r9,r,r mul r6,r7,r8 after Condition: beq must be independent of add. Result: Always saves a clock. Lecture 5-: Branch Hazards 5--2/6 /5/24 A. Sohn

7 Before Filling in the Slot add r,r2,r3 beq r2,r3,target or r9,f,r target+: mul r6,r7,r8 Clock Lecture 5-: Branch Hazards 5--3/6 /5/24 A. Sohn After Filling in the Slot load r6,(r7) beq r2,r3,target add r,r2,r3 target+: mul r6,r7,r8 Clock Lecture 5-: Branch Hazards 5--4/6 /5/24 A. Sohn

8 Delayed Branch load r6, (r7) mul r6,r7,r8 add r,r2,r3 nop or r9,r,r before load r6, (r7) target: mul r6,r7,r8 add r,r2,r3 sub r4,r5,r6 or r9,r,r after Condition: must be ok if not taken. Result: Saves clock if the branch is taken. Lecture 5-: Branch Hazards 5--5/6 /5/24 A. Sohn Delayed Branch add r, r2, r3 nop sub r4,r5,r6 or r9,r,r target: mul r6,r7,r8 before add r, r2, r3 sub r4,r5,r6 or r9,r,r target: mul r6,r7,r8 after Condition: must be ok if the branch is taken. Result: saves a clock if the branch is not taken. Lecture 5-: Branch Hazards 5--6/6 /5/24 A. Sohn