Lecture Topics. Overview ECE 486/586. Computer Architecture. Lecture # 9. Processor Organization. Basic Processor Hardware Pipelining

Transcription

1 EE 486/586 ompute chitectue Lectue # 9 asic Pocesso Hadwae Pipelining Refeence: ppendix : Section.1 Lectue Topics Sping 2015 Potland State Univesity Oveview Pocesso Oganization typical computing task consists of a sequence of instuctions that constitute a pogam Pocessing Unit (pocesso) caies out these instuctions n instuction is pocessedby pefoming a sequence of moe udimentay opeations, such as: Fetching the instuction fom memoy ecoding the instuction to undestand its semantics Executing the instuction iffeent pocesso achitectues diffe in the way they pefom the above opeations MR P IR Memoy MR R 0 R 1 ontol LU Read/ Wite Pocesso R N-1 N geneal-pupose egistes

2 Pocesso Registes Instuction Pocessing Steps Instuction egiste (IR) Holds the instuction that is cuently being executed Pogam counte (P) ontains addess of the next instuction to be fetched/executed Geneal-pupose egiste (R 0 R n-1 ) Hold opeands that ae cuently being (o soon to be) pocessed Initial State:P is set to point to the fist instuction Fo each instuction, pefom the following 5 steps: Instuction Fetch (IF) Instuction ecode/registe Read (I) Execution/Effective ddess alculation (EX) Memoy ccess (MEM) Wite ack (W) 5 Pocessing Steps Instuction Fetch: Send P to memoy, asset MemReadsignal Instuction ead out fom memoy Place instuction in IR Update P to next instuction: P [P] + 4 Instuction ecode: Instuction in IR decoded by contol logic, instuction type and opeands detemined Souce opeand egistes ead fom geneal pupose egiste file 5 Pocessing Steps (cont.) Execute: LU opeates on opeands pepaed in pevious cycle One of fou functions depending upon opcode Memoy Refeence Fom effective addess fom base egiste and immediate offset LUOutput + Imm Registe-Registe LU Instuction LU Output func Registe-Immediate LU Instuction LU Output funcimm anch ompute banch taget by adding Immto P LU Output P + (Imm<< 2) Evaluate the banch condition

3 5 Pocessing Steps (cont.) asic Pocessing Hadwae Memoy ccess: Fo load instuctions, ead data fom memoy Fo stoe instuctions, wite data to memoy Witeback: Results witten to destination egiste Registe stage Registe stage lock peiod must be longe than the delay of the combinational logic cicuit Registe stage Multi-stage Pocessing Hadwae Registe stage 5-stage MIPS Pocesso Fetch ecode Execute Memoy ccess Witeback ombinational cicuit boken down into multiple stages, each taking one clock cycle If thee ae nstages, clock peiod is 1/nof the clock peiod on pevious slide Inte-stage egistes hold a stage s esult, so they can be used as next stage s inputs FETH: Fetch an instuction and incement the P EOE: ecode the instuction (detemine instuction type, souce & destination egistes) and ead souce egistes fom egiste file EXEUTE: Pefom an LU opeation MEMORY ESS:Read o wite memoy data if the instuction involves a memoy opeation WRITEK: Wite the esult into the destination egiste, if needed

4 ithmetic and Logic Instuctions Example with only egiste opeands dd R3, R4, R5 Souce egistes: R4, R5 R3 [R4]+[R5] estination egiste: R3 Instuction steps: Fetch: Fetch the instuction and incement the pogam counte ecode: ecode the instuction in IR to detemine the opeation to be pefomed (add). Read the contents of egistes R4 and R5 Execute: ompute the sum [R4] + [R5] Memoy ccess: No action, since thee ae no memoy opeands Witeback: Wite the esult into egiste R3 Load Instuctions Example Load R5, X(R7) R5 [[R7]+X] Souce egiste: R7 estination egiste: R5 The immediate value X is given in the instuction wod Instuction steps: Fetch: Fetch the instuction and incement the pogam counte ecode: ecode the instuction in IR to detemine the opeation to be pefomed (load). Read the contents of egiste R7. Execute: dd the immediate value X to the contents of R7 Memoy ccess: Use the sum X+[R7] as the effective addess of the souce opeand, ead the contents of that location fom memoy Witeback: Wite the data eceived fom memoy into egiste R5 Stoe Instuctions Example Stoe R6, X(R8) X+[R8] [R6] Souce egistes: R6, R8 estination egiste: None The immediate value X is given in the instuction wod Instuction steps: Fetch: Fetch the instuction and incement the pogam counte ecode: ecode the instuction in IR to detemine the opeation to be pefomed (stoe). Read the contents of egistes R6 and R8. Execute: ompute the effective addess X + [R8] Memoy ccess: Stoe the contents of egiste R6 into memoy location X + [R8] Witeback: No action How to Impove Pefomance? So fa, we have assumed that only oneinstuction is being pocessed by the multi-stage hadwae at any point of time How do we decease the execution time of a pogam? One possibility is to use faste cicuits to implement the pocesso This appoach will decease the execution time of each instuction nothe possibility is to aange the pocesso hadwae in such a way that multipleinstuctions can be pocessed at the same time. This appoach is called pipelining Pipelining does not change the time needed to pefom a single instuction, but it inceases the numbe of instuctions pefomed pe second (instuction completion ate o thoughput)

5 Pipelining: Example fom aily Life Pipelining: Example fom aily Life (cont.) Laundy Example 6 PM Midnight Fou loads of laundy need to be washed, died and folded Washe takes 30 minutes Sequential laundy takes 6 hous fo 4 loads If pipelining is used, how long would laundy take? ye takes 40 minutes Folde takes 20 minutes Pipelining: Example fom aily Life (cont.) Pipelining: Example fom aily Life (cont.) T a s k O d e 6 PM Midnight Pipelined laundy takes 3.5 hous fo 4 loads T a s k O d e 6 PM Pipelining doesn t educe the time taken by an individual task, it impoves the thoughput of entie wokload Task completion ate limited by slowest pipeline stage Potential speedup = Numbe of pipeline stages Unbalanced lengths of pipeline stages educes speedup to fill pipeline and time to dain it educes speedup