Design and Technology Solutions for Development of SiGeMEMS devices. Tom Flynn Vice President, Sales Coventor

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1 Design and Technology Solutions for Development of SiGeMEMS devices Tom Flynn Vice President, Sales Coventor

2 Special thanks to: Stephane Donnay, Program Manager, imec Gerold Schropfer, Director, Foundary Programs, Coventor Raffaella Borzi, Director, Business Development, imec Contact info: and

3 Outline Introduction MEMS and IC, CMORE Technology MEMS design environment Traditional approach and new structured approach to MEMS-IC MEMS SiGe Process Design Kit (PDK) SiGe MEMS resonator example Design, simulation and silicon realization Summary and outlook

MEMS and IC design flows Leads to long development cycles and high costs

4 About MEMS MEMS are micro- or nano-scaled devices typically comprised of Sensing or actuation device Integrated electronics Disconnect between MEMS and IC design flows Leads to long development cycles and high costs Minimal design reuse imec & Coventor have teamed to address this critical need

die MEMS CMOS SIP: F2F MEMS IC CMOS SIP:

5 CMORE SiGeMEMS Technology: 1. MONOLITHIC INTEGRATION WITH IC Different MEMS-IC Integration approaches InvenSense IMEC Approach SIP: Stacked die MEMS CMOS SIP: F2F MEMS IC CMOS SIP: 3D vias MEMS SoC: monolithic MEMS CMOS Interconnect pitch ~ 50 um ~10um ~10um ~1um Interconnect parasitics few pf >100fF <100fF few ff yield KGD KGD (unless W2W) KGD (unless W2W) compound yield Monolithic approach: Most compact solution Better intrinsic system reliability: less components, less interconnections Best solution for applications that are very sensitive to parasitics

processing No thermal limitations T-budget 800 C T-budget 450 C CMOS Non-standard Non-standard any standard CMOS Interconnections MEMS-IC

6 CMORE SiGeMEMS Technology: 2. MEMS LAST (ABOVE CMOS) Different Monolithic MEMS approaches SiTime ADI IMEC Approach MEMS first intracmos MEMS last MEMS MEMS MEMS MEMS MEMS processing No thermal limitations T-budget 800 C T-budget 450 C CMOS Non-standard Non-standard any standard CMOS Interconnections MEMS-IC Peripheral around MEMS Peripheral around MEMS Distributed & massively parallel MEMS last: most flexible with respect to choice of CMOS technology very high-density and massively parallel interconnections possible enabling large arrays of MEMS (e.g. μmirror arrays)

7 CMORE SiGeMEMS Technology: 3. POLY-SiGe IMEC Approach Different Above CMOS MEMS approaches Al TI Poly-SiGe Post CMOS integration yes yes Fracture strength [GPa] 0.2 > 2 Mechanical Q low > Reliability creep: hinge memory effect No creep Poly-SiGe: better mechanical properties than Al: higher strength and Q factor better reliability properties than Al: less creep and fatigue

8 CMORE MEMS Technology: 4. FLEXIBLE & MODULAR TECHNOLOGY FLOW Monolithic Above-IC SiGe-based Flexible MEMS technology Capping layer (SiGe) Electrode (Bottom - SiGe) Sealing Electrode (Top - SiGe) Metal (Al) Mechanical layer (Bottom - SiGe) Mechanical layer (Top - SiGe) Sealing & connections Capping & sealing layer Capping layer Mechanical layer MEMS structural layer Electrode layer Plug Electrode layer CMOS wafer On top of any CMOS (on 200mm) Surface micromachining on top of CMOS: temperature limited 450 o C for Al interconnections Poly-SiGe deposited at 450 o C E=140 GPa (60-70 at.% Ge) Stress = ~0-70 MPa Strain gradient = ± /μm (4 μm thick CVD+PECVD SiGe) Poly-Si: 620 o C deposition, 800 o C needed for desired stress Oxide Sacrificial oxide CMOS top metal layer Plug Protection layer (SiC) Flexible and modular technology: Variable layer thicknesses Application-specific optimization of layer & material properties Application-specific functional add-on layers

9 Design Challenge Device Design and Simulation Tools IC Design and Simulation Tools IC designers require an accurate MEMS model for system simulation and layout.

Partnership Industry Eco-System MEMS Design Platform CMORE- MEMS Fabrication Platform Establish Industry Standard Solution for MEMS and MEMS System

10 Partnership Industry Eco-System MEMS Design Platform CMORE- MEMS Fabrication Platform Establish Industry Standard Solution for MEMS and MEMS System Design (MEMS+IC ) Integration and standardization of a MEMS+IC design flow Fabrication access via MEMS process design kits Lower risk, improve time-to-market

11 MEMS design environment

12 MEMS+ with Cadence Virtuoso

13 Integration with Cadence MEMS+ takes full advantage of the Cadence Virtuoso custom IC design environment Parametric MEMS + Design MEMS-IC Simulation Monte-Carlo and Yield Analysis Parasitic Capacitance Extraction Combined DRC Signoff

14 MEMS+ Component Library

15 Process and Material Variables MEMS is quite different from IC Design Customized or semi-customized processes are common; e.g., MEMS designer might be able to change a structural layer thickness within limits MEMS component models like suspensions, combs and electrodes are not foundry specific Varying process and material data are key for PDK usage, e.g. yield analysis With the imec/coventor Solution, all process and material variables are seamlessly linked to MEMS+ component models

16 Process Editor Captures MEMS process sequence Allows to define process variables as design variables (e.g. thickness of layers) Directly linked to library models MEMS+ Process Editor with imec SiGe MEMS process

17 Material Database Editor MEMS specific data e.g. Young s modulus, stress etc. Specific to fab/process Measured, calibrated MEMS+ Material Database for imec SiGe MEMS process

18 Design example: SiGe MEMS resonator

19 MEMS Resonators Flexural mode resonance Distributed spring and mass Extensional mode resonance Extremely high quality factors Slab of material used in breathing mode, analogy with EM cavity resonators SANDIA Berkeley imec

T-Support Geometry Bar resonator Electrostatic actuation, transduction of electrical energy to acoustic energy Design frequency 24 MHz T-shaped supports Provides

20 T-Support Geometry Bar resonator Electrostatic actuation, transduction of electrical energy to acoustic energy Design frequency 24 MHz T-shaped supports Provides stability in direction of actuation direction, allowing high bias voltages Can be optimized in terms of support losses, i.e. quality factor Possibility to have relatively long legs without penalty with regards to quality factor allows thermal heating or isolation from the substrate Anchor Connection width Connection length Anchor Schematic Diagram Electrode Bar length L Resonator Bar width W Electrode SEM Image of device Anchor Support length (L Tsup ) Support width Anchor Extruded resonator

components from the library to assemble the device

21 Resonator Model Construction The MEMS designer starts with a blank, 3-D canvas The MEMS designer picks components from the library to assemble the device Component parameters can be defined as values, variables or equations

22 Process Dependent MEMS Model Each component can be assigned to layer(s) of corresponding PDK process

23 Integration with Cadence Several views of MEMS device in Virtuoso library manager

S21 (db) Frequency Analysis in MEMS+ Model

shape effected by the Poisson ratio -60-70

24 S21 (db) Frequency Analysis in MEMS+ Model Buildup 4 th order rectangular plate component Multiple sections for supports, capturing higher order flexural modes Simulation results Mode shape effected by the Poisson ratio Frequency (Mhz)

25 Frequency Analysis in MEMS+ Result Visualization of Mode of Interest at 23.8MHz (Displacement Exaggerated)

S21 (db) S21 (db) Experimental Validation MEMS+ Model in Cadence Quality factor tuned in Virtuoso with resistor to match known value Validation Simulations match measurements closely, both in terms

26 S21 (db) S21 (db) Experimental Validation MEMS+ Model in Cadence Quality factor tuned in Virtuoso with resistor to match known value Validation Simulations match measurements closely, both in terms of resonance frequency and transmission levels Frequency (Mhz) Measured results Frequency (Mhz) Simulated results

27 Summary and Outlook

28 : MEMS+ - A Hub for MEMS Design SEMulator3D Process Emulation Algorithm Level Design MEMS+ System Design CoventorWare FEM Damping and Stress Analysis Structural Level Design and PCell Generation

29 IMEC SiGe Design Kits (initial versions available from imec or Coventor) MEMS Design MEMS + IC Co-Design MEMS+ Platform MEMS Design Verification (FEA) CoventorWare Design Review Manufacturability Check Documentation and Training SEMulator3D

30 Additional Examples IMEC s SiGe technology and Coventor s MEMS+ platform can be used to develop a variety of MEMS designs μmirror arrays (ring) gyros probe memory accelerometers

18 HV CMOS Open for external designers Layout submission end of 2011 Training workshop on SiGe MEMS process and PDKs September 2011

31 Next PDKs and MEMS SiGe runs Next version of MEMS SiGe PDKs will support More process types, e.g. flexibility on mechanical layer thickness Compatibility to CMOS PDK Upcoming SiGe MEMS Multi-Project-Wafer run TSMC 0.18 HV CMOS Open for external designers Layout submission end of 2011 Training workshop on SiGe MEMS process and PDKs September 2011 Thin SiGe platform structural layer thickness: 300nm gap: nm actuation gap: 300 nm coating for optical properties Thick SiGe platform structural layer thickness: 4μm nanogaps: nm

32 Thank You!

TEPZZ A_T EP A1 (19) (11) EP A1 (12) EUROPEAN PATENT APPLICATION. (51) Int Cl.: G01L 9/00 ( )

TEPZZ A_T EP A1 (19) (11) EP A1 (12) EUROPEAN PATENT APPLICATION. (51) Int Cl.: G01L 9/00 ( ) (19) TEPZZ 796844A_T (11) EP 2 796 844 A1 (12) EUROPEAN PATENT APPLICATION (43) Date of publication: 29..2014 Bulletin 2014/44 (51) Int Cl.: G01L 9/00 (2006.01) (21) Application number: 13165416.2 (22)