2004 ITRS Update ORTC Economics and Technology Overview

Transcription

1 2004 ITRS Update ORTC Economics and Technology Overview Nodes, Chip Size, Transistors, Capacity, $ Trends Alan Allan/Intel Corp 11/16/04 IMAPS GBC Marketing Forum [Final Draft] 1

2 2004 (2004 ITRS Exec. Summary and ORTC ) it s all about: Economics + Technology and Customers, who Buy Products (emulated and mapped to chips) which, though the customers don t know or appreciate it, need Semiconductor: Nodes Chip Sizes Transistors Capacity $ 2

3 Clear Both Economics + Technology Hurdles = Growth 90 s 21st Century Economics Technology Semiconductor Industry Semiconductor Industry 3

4 Wanted: CUSTOMERS, who breathe, eat, and live in.. Global & Regional Political & Macro-Economic Environments and who BUY, based on varying levels of Purchasing Power, PRODUCTS Customer Demand Electronic End Equipment Semiconductors Sources: NASA.gov ; SEMI Semiconductor Equipment Equipment & Materials Materials Ecosystem or Foodchain? 4

5 Semiconductors is the key enabler for wealth creation Traditional (drivers) SERVICES (new drivers) Computer Consumer Automotive Communications Industrial / Medical Defense / Aerospace $5000B $1000B Electronic industry Internet service providers Communication services Broadcasters $166B Semiconductor industry Source: STMicroelectronics (2003 data) SUPPORT INDUSTRIES Fab equipment $28B Materials $21B EDA $3B 5

6 Products (As Defined by NEMI PEGs*) * Product [Need] Emulator Groups 6

7 Drivers Medical Automotive Office Network Portable Defense [Industrial] Applications (NEMI) SIP/SOC SIP/SOC (ITRS) A 4 A 3 A 2 A 1 Architectures AMS MPU Memory DSP Chips /Fabrics (ITRS) Source: ITRS Design TWG Figure 1: Potential mapping approach between NEMI and ITRS roadmaps 7

8 Cell Phone Unit Forecast (Annual, Asia/Pacific) According to industry analysts, China is a market poised for major growth in cell phone use. Some analysts estimate that by 2006 China will have about 385 million cellular customers History WAS (China) Forecast IS (World) Total WWide Cell Phone Units (M) Despite an inventory overhang in China, isuppli Corp. (El Segundo, Calif.) is increasing its worldwide cellular phone shipment forecast to 675 million units in 2004, up from 670 million previously. This represents 18 percent growth compared to 2003 [572Mu], according to the market research firm Source: Komatsu : Source: 279CADB B ? OpenDocument 8

9 Cumulative PC Units PC s Unit Forecast (Cumulative, W.Wide) 2B 1B The industry analyst firm Gartner Dataquest announced this week that the PC industry has shipped the 1 billionth PC. The industry reached this milestone in April 2002, roughly 25 years after the debut of the first commercially successful and widely available personal computer, the 1974 Altair. Gartner Dataquest calculates that the next billion PCs could ship far faster than the ones that came before. In 2008, the PC industry is projected to reach the milestone of 2 billion PCs, with the greatest growth opportunity coming from high-volume emerging markets in places such as China, Latin America, and Eastern Europe History Ave: 75M/yr Forecast Ave: 160M/yr Ave: 13M/yr Source: Gartner DataQuest Statement, July 2002; (plus aka interpolation/extrapolation linear/smooth curve analysis) 9

10 WiFi Unit Forecast (Cumulative, W.Wide)..Today, we are in the early stages of sharing. Last year 33.2 million units were shipped. Semico predicts the market to reach 415 million units by Semico Research, New Industry Research May 5, 2004 Report# DH History Forecast [67% CAGR] 10

11 Nodes 11

12 Fig 2 Production Ramp-up Model and Technology Node Volume (Parts/Month) 100M 10M 1M 100K 10K 1K Development Alpha Tool Beta Tool Production Tool First Conf. Papers Production First Two Companies Reaching Production 2 200K 20K 2K Volume (Wafers/Month) Source: 2003 ITRS - Exec. Summary Fig 2 0 Months

13 Technology Nodes: Back to 3-year cycle Near Term Long Term Year of Production Technology Node [DRAM] (nm) 2002 [Actual] hp hp hp hp hp hp Year Technology Cycle [ actual] 3-Year Technology Cycle Source: 2003 ITRS - Exec. Summary Table C 13

14 [DRAM Half-Pitch] 3-year Node-Cycle 2-year Node-Cycle [DRAM] Company A Company B Company C year Node-Cycle Source: STRJ, ITRS PIDS ITWG Survey, ca. 2Q ITRS 2003: 2003/100(-110nm?) /16nm: Average 0.5x/2.5years 14

15 2004 ITRS Renewal ORTC Table Header/ Targets (unchanged fr. 03): 2003 ITRS Technology Node Header (**Unchanged from 2001/2002 ITRS): DRAM HP Actual hp180 hp130 Near-Term Long Term Notes hp90 hp65 hp45 hp32 hp22 DRAM Unchanged * 50* 45 35* 32 25* 22 18* Other ORTC Tracked Technology Trends (optional - use by TWG Tables as needed): Poly Unchanged * 50* 45 35* 32 25* 22 18* NEW Logic M1: UNCHANGED: MPU Pr GL: * 28* * * * MPU Ph GL: * 20* * * 9 8 7* ** *** * Not visible in 2001 ITRS due to no annual columns between "Near Term" and "Long Term" column ranges. The 2001 ITRS Long Term columns are retained for continuity of technology nodes. ** DRAM Half-Pitch Nodes unchanged, however cell design factor improvement has been significantly delayed in the 2003 ITRS. Node timing is based on original 2001 ITRS glossary definition of 10Ku/mo manufacturing with Production-Capable Equipment and Materials. *** Note: Logic Half-Pitch (HP) was based on Un-contacted Logic Poly HP in 2001 ITRS. In the 2003 ITRS, Logic Metal 1 (M1) was added and correlated with IC TWG Local Wiring Pitch/2 [120nm/2003, plus a 3-year target cycle trend]. 15

16 Chip Sizes 16

17 ITRS DRAM Chip Size Model (Rev 1, 07/23/03) 16G 8G 32G 64G Max Affordable Litho Field 2003 ITRS: 704mm2 (22x32) Max Affordable Litho Field 2001 ITRS: 572mm2 (22x26) 500 4G 128G 256G 1T (mm2) Bits/ chip: 256M 1G 512M Bits/ 200 chip: 64M 128M 256M 100 Cell 2G 512M 1G 2G 4G 8G 16G 32G 64G Factor: Node: Year of Introduction and Production 128G Cell Area Efficiency (CAE) = 63-73% Intro Chip Size (mm2) Prod Chip Size (mm2) Cell Area Efficiency (CAE) = 63% 4 chips per Max Affordable Litho 572mm2 = 143mm2 (22x6.5) 5 chips per Max Affordable Litho 704mm2 = 141mm2 (22x6.4) 17

18 MPU Chip size (mm2) Historical Trends vs Unchanged ITRS Model* mm2 Litho Field Size New: 704mm2 Litho Field Size 572mm2 Litho Field Size 286mm2 2 per Field Size HP MPU 310mm2 CP MPU 140mm2 100 CP Shrink 70mm2 *1999 Leading- Edge.18u HP MPU: 2MB (113Mt [81.9%] x 1.18u2/t = 135mm2) + 25Mt Logic x 5.19u2/t = 130mm2 + 45mm2 OH= 310mm2 = Total 138Mt x ave 2.25u2/t = 310mm2 *1999 Leading- Edge.18u CP MPU: 512KB (28Mt [58.3%] x 1.18u2/t = 34mm2) + 20Mt Logic x 5.19u2/t = 104mm2 + 2mm2 OH= 106mm2 = Total 48Mt x ave 2.92u2/t = 140mm2 * ITRS Design TWG MPU Transistors/Chip Model: ~2x/Node = 2x/2yrs from ; then 2x/3yrs from

19 Transistors 19

20 Transistors VLSI Research May 03 [source: tci030509graphicsspcl2.xls] [Transistors] Units 1E+18 1E+17 1E+16 1E+15 1E+14 1E+13 1E+12 1E+11 1E+10 1E+09 1E+08 Worldwide Transistor Production There's no slowing of Moore's Law here! [ (1e3)^(1/16yrs) = 54% Ave CAGR] RESTRICTED DATA: for access and use only w ithin your company, as per your company's agreement w ith VLSI Research Inc. Copyright 2003 by VLSI Research Inc. 20

21 Transistors VLSI Research May 03 [source: tci030509graphicsspcl2.xls] Integrated Circuit (IC) TI & Fairchild ca Moore s 2x/1yr Original G. Moore Paper Electronics, 4/19/65: 2X/1YR Components Per Integrated Circuit (aka Functions/Chip) That means that by 1975 the number Of components per integrated circuit for Minimum cost will be 65,000 Moore s 2x/1.5-2yrs ITRS -- Long Term Moore s 2x/3yrs ITRS -- Near Term Moore s 2x/2yrs You are Here! Zeta-Xistors (1e21) Transistors/Chip 1Tt 1e11 1e10 1Gt 1e08 1e07 1Mt 1e05 1e04 1Kt t 1946 [Transistors] Units E+18 1E+17 1E+16 1E+15 1E+14 1E+13 1E+12 1E+11 1E+10 1E+09 1E In the beginning Bell Labs ca Worldwide Transistor Production RESTRICTED DATA: for access and use only w ithin your company, as per your company's agreement w ith VLSI Research Inc. Copyright 2003 by VLSI Research Inc There's no slowing of Moore's Law here! Pt Est. from Semico: 1997 SubTotal: 2.88 Product Transistors (Pt) MCU 0.84 Semico (SIA): 1997 SubTotal: Discrete MPR 0.36 Product Units (B) MCU 4.20 Analog DRAM 42.9 Discrete MPR 1.80 Other Memory 0.98 Flash 1.71 Analog DRAM 3.30 Other Logic 1.78 MPU 0.78 Other Memory 3.90 Flash 0.57 SubTotal: 2.88 Total: Other Logic MPU 0.26 SubTotal: Total: [ (1e3)^(1/16yrs) = 54% Ave CAGR] Exa-Transistors (Et) 1e Peta-Transistors (Pt) 1e15 Tera-Transistors (Tt) 1e12 Giga-Transistors (Gt) 1e09 2x/2years 1969 (1K) 2020 (32G) Mega-Transistors (Mt) 1e ITRS Timeframe 20 Kilo-Transistors (Kt) 1e03 One-a-Transistor (t) 1e00 2x/3yrs (1G/ 05-32G/ 20) 21

22 Capacity 22

23 Fig 3 Feature Size (Half Pitch) (µm) p350 Technology Node Compared to Actual Wafer Production Capacity Technology Node Distribution Feature Size of Technology W.P.C.= Total Worldwide Wafer Production Capacity (Relative Value *) W.P.C <0.4µm W.P.C <0.4µm W.P.C 2 5 % 2 5 % SIA/SICAS Data: 1-yr delay from ITRS Timing to 25% of MOS IC Capacity hp250 <0.3µm Source: 2003 ITRS - Exec. Summary Fig 3 W.P.C <0.3µm W.P.C <0.2µm Year W.P.C <0.2µm ITRS Technology Node hp % W.P.C 25 % <0.16µm Source: SICAS** * Note: The wafer production capacity data are plotted from the SICAS* 4Q data for each year, except 2Q data for The area of each of the production capacity bars corresponds to the relative share of the Total MOS IC production start silicon area for that range of the feature size (y-axis). Data is based upon capacity if fully utilized. hp90 hp65 ctual Actual Actual Actual 3-Yr 2-Yr 3-Yr ** Source: Semiconductor Industry Capacity Statistics (SICAS) collected from worldwide semiconductor manufacturers (estimated >90% of Total MOS Capacity) and published by the Semiconductor Industry Association (SIA), as of July, 2003 hp %? >0.7µm hp720nm µm hp510nm µm hp360nm µm hp255nm µm hp180nm <0.16µm hp127nm <0.11um F cast 23 hp90nm

24 ISMT/IEM [Semico] IC Product Technology Profile 1.00 SICAS Node* >25% of MOS IC Capacity nm 910 nm 560 nm LEM: DRAM Flash LEL: MPU DSP 820 nm 460 nm 255nm 770 nm 400 nm 690 nm 180nm OLE: Graphics ; Std Cell; PLD; MROM; Chipsets; SRAM; Comm; MCU 140nm OIC: EPROM; Mass Storage; Gate Arrays; 127nm Voice and Other; EEPROM; Std Logic; Analog / Linear nm ITRS hpxx (Actual); PrGl ; PhGL Other IC Average Leading Edge Mfg Roadmap Node * SICAS Most Leading Edge Node Range** = 25-30% of MOS IC Area, Actual All Leading Edge Average ** Examples: 180nm = 0.22u-0.18u-0.15u; 130nm = 0.15u-0.13u-0.11u; 90nm = 107nm-90nm-75nm 290 nm LEM, LEL L.Edge Average 650 nm 225 nm 65 nm 45 nm 24

25 $, Gestalt 25

26 Macro Overview GWP, Revenue, Capacity Demand Snapshot As of 10/23/02 Bilion Dollars ($B); Silicon Sq.In. (Msi/1e4); #Wafers (w / NPW) (Mu/1e4) 1.E+05 1.E+04 1.E+03 1.E+02 1.E+01 1.E+00 1.E-01 1.E-02 1.E-03 Source: VLSIR, April, Sept World Electronics, Semi, Tools, Si Area, #Fabs, Wafer Units vs. GWP ($B) 00 WAS: 29% % % 1 Tera-Dollar 8.26% $ USA GDP AVE ~3-4% 10% CAGR? % Tool Sales ($B) Chip Sales ($B) Electronics Sales ($B) GWP ($B) Silicon Sq. Inches (Msi/1e4) Silicon Wafers (Mu/1e4) Total # Fabs (20Kwspm - #/1e04) 1984 $ % 15.5 % 1% History <-2000-> F'cast 10% 2.8% 0-1%? % $ %? %? 2002 $45T $10T $1.1T $.22T $.045T %? $

27 Electronics Chips Chip Equipment Hi-Tech Revenues Worldwide [VLSIR ca May 03] 02 WAS: Past < [~7.5% CAGR] [~15.5% CAGR] (Revenues in $M) Chips and Equipment have been tracking Electronics growth rates since 1995, albeit with higher volatility. RESTRICTED DATA: for access and use only w ithin your company, as per your company's agreement w ith VLSI Research Inc. Copyright 2003 by VLSI Research Inc. 27

28 VLSIR History: CAGR = 6.8% CAGR = 5.6% Revenue Past Future Estimate: CAGR = 5.8% ($M) % CAGR 7% -7.5%CAGR Sources: VLSI Research ( ), Electronics Consultant ( ) Year Semiconductor Equipment Semiconductor Electronics 28

29 Microcents 1.E+06 1.E+05 1.E+04 1.E+03 1.E+02 1.E+01 1.E+00 1.E-01 ITRS Ave Cost per Function vs. Industry Ave Price per Function vs. Estimated #Industry Transistors (Final Packaged Unit) Milli- Dollar (m$) DRAM Ave Price/bit (VLSIR) -29.3%ave CARR Sources: Past: VLSI Research ca May '03 Future: ITRS Industry Ave Price/Xistor (VLSIR) Micro- Dollar (u$) Peta-Transistors (Pt) 46.8% CAGR Industry Est. Xistor Demand (VLSIR) Nano- Dollar (n$).36u Year 66.8% CAGR Past <---> Future 46.8% % CAGR?? Exa-Transistors (Et) MPU Ave Price/Xistor 65%Gross Margin) DRAM Ave Price/Bit Tera-Transistors (Tt) 35% Gross Margin) 1e 1.E Node: $ 5.6u 2.8u $ -25.0%ave CARR '75-'99 then -29.3%ave 1.4u.72u $ 54.6%ave CAGR 1e u 90n 45n 22n 16n $ # Transistors 1e +20 1e +19 1e +18 1e +17 1e +16 1e +15 1e +14 1e +13 Zetta-Xistors (Zt) DRAM cost/bit - intro (@ 35% Ave Gross DRAM cost/bit - prod (@ 35% Ave Gross Cost-perf MPU - intro (@ 65% Ave Gross Cost-perf MPU - prod (@ 65% Ave Gross High-perf MPU - prod (@ 65% Ave Gross 2019/16nm Node $1T, ~10% CAGR from $145B/

30 What Can History Teach Us? 7 th Wave? Total Semi Revenue $1T $0.5T Growing to $1T will require a few more Waves of emerging Applications, Economies, and Customers! (and, yes, a couple more wafer generations or equivalent productivity improvements!) You Are Here! 5 th Wave? 6 th Wave? 10% 7.5% Total Semi Revenue Wafer Size Total Semi 2003: $166B Source SIA/WSTS Analog Wave TV, VCR Internet Wave Internet Boom, Cell Phones Digital Content Digital Wave Personal Computing Portability & Connectivity Wave Multiple Wireless Devices Fuel Cells, Rich Media / 4 5 / 6 200mm 300mm 450mm 675mm 30 Source: Semico Research Corp, May 04

31 Summary ITRS Node timing [DRAM Half-Pitch based] is based on the first two leading-edge companies beginning manufacturing ramp ITRS Nodes [DRAM Half-Pitch based] are forecast to slow from the present 2-year to a 3-year pace after 2003, and slowing design factors are causing density to double only every technology node Leading-edge DRAM Product first production start Chip Sizes are targeted to remain flat at about 140mm2 for affordability, but will shrink further in size To keep chip sizes affordable [ie flat ], the ITRS target Moore s Law DRAM functionality per chip is slowing from 2x/1.5-2yrs to 2x/2.5-3yrs; However, Average Moore s Law should remain 2x/2yrs through 2020 Leading-edge volume Capacity Demand, as monitored by SICAS, is on the same 2-year pace as the ITRS nodes, with the 130nm technology range (<150nm to >110nm) reaching >25% of MOS IC capacity in

32 Summary (cont.) There appears to be no slowing in the overall demand for transistors, which has averaged over 50% compound growth since the 70 s a pace which increases demand 1000 times every 16 years To keep the cost per transistor and per bit affordable to enduse applications and consumers, the cost to manufacture transistors inside finished semiconductor devices must decrease at an average -29% compound rate The ITRS targets the affordable cost per function reduction target is based on a historical target of -29%, and if this cost reduction can be maintained as demand for total transistors grows at a 53-55% rate, the revenue of the industry could grow at % per year, reaching $1T by from the 1999 level of $145B Of course, growing to $1T will require more emerging Waves of end-application demand and continous manufacturing productivity improvements! 32