TKT-2431 Soc Design. Lec 11 Energy consumption. Department of Computer Systems. Tampere University of Technology

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1 TKT-2431 Soc Design Lec 11 Energy consumption Erno Salminen Tampere University of Technology Fall 2012 Remember the guest lecture Mon Erno Salminen - Nov. 2012

2 Contents Power consumption breakdown Low-power design at system level Dynamic power management (DPM) Clock gating, power supple shutdown Dynamic voltage/frequency scaling Low-power operating modes Prediction methods #2/67 Erno Salminen - Nov. 2012

3 Copyright notice Part of the slides S. Dey, VLSI Advanced Topics, course material, UCSD Part of figures from L. Benini, A. Bogliolo, G. De Micheli, A Survey of Design Techniques for System-Level Dynamic Power Management, TVLSI, Vol. 8, No. 3, June 2000, pp #3/67 Erno Salminen - Nov. 2012

4 At first Make sure that simple things work before even trying more complex ones You should believe this by now... #4/67 Erno Salminen - Nov. 2012

5 Descriptive citation (one of many ) The power problem is the No. 1 issue in the long-term for computing. It's time for us to stop making 6-mileper-gallon gas guzzlers. [ ] Now you're going to see the great unmarketing of megahertz because it doesn't matter anymore.'' Greg Papadopoulos, Chief Technology Officer for Sun Microsystems, Chip Makers Feel Heat to Solve Power Problem, San Jose Mercury News, July 2nd 2004 #5/67 Erno Salminen - Nov. 2012

6 The big 4 (reasons) asd PS. ICT accounts ~2% of world electricity consumption Some researchers say that this problem is exaggerated, but I did ot find a good reference on short notice - ES S. Dey, Design of Low-Power, Battery-Efficient Systems, ECE206C course material, UCSD, #6/67 Erno Salminen - Nov. 2012

7 Trends (1): Batteries do get better But batteries evolve at much lower rate than other parts Fig: [John Hockenberry, Building a better battery, Wired, iss , Nov 2006] HD CPU battery #7/67 Erno Salminen - Nov. 2012

8 Trends (2) : Cooling cost reaches computer cost in datacenters [G. Lawton, Powering Down the Computing Infrastructure, Computer, Vol. 40, Iss. 2, Feb. 2007, pp ] #8/67 Erno Salminen - Nov. 2012

9 Power consumption breakdown Erno Salminen - Nov. 2012

Examples A large and increasing number of devices are battery driven Desktop PCs (100-300 W) Datacenter (25MW) Rack server (5-10kW)

10 Examples A large and increasing number of devices are battery driven Desktop PCs ( W) Datacenter (25MW) Rack server (5-10kW) W S. Dey, Design of Low-Power, Battery-Efficient Systems, ECE206C course material, UCSD, #10/67 Erno Salminen - Nov. 2012

11 Power breakdown: laptop S. Dey, Design of Low-Power, Battery- Efficient Systems, ECE206C course material, UCSD, J. Faludi, Green Computing Update, Part 2: Components, WorldChanging.com, 16 Nov 07 #11/67 Erno Salminen - Nov. 2012

Example high-end SoC 16 SPARC cores, 6MB L2 cache 40nm, 11 Cu metals, 377 mm 2, 1G transistors 1.

, A 40 nm 16- Core 128-Thread SPARC SoC Processor, IEEE Journal of Solid-State Circuits, Vol.

12 Example high-end SoC 16 SPARC cores, 6MB L2 cache 40nm, 11 Cu metals, 377 mm 2, 1G transistors GHz, 120W 1284 power pins on the chip! 6 clock domains 7 power domains [J.L, Shin et al., A 40 nm 16- Core 128-Thread SPARC SoC Processor, IEEE Journal of Solid-State Circuits, Vol.46, Iss. 1, 2011, pp ] Power per block Dynamic power per circuit element #12/67 Erno Salminen - Nov. 2012

Sources of power consumption Dynamic power dominates in logic Leakage power dominates in memory Small activity Dynamic: access one 32b word at a time in 32MB memory Leakage: in all other 32MB-4B mem

13 Sources of power consumption Dynamic power dominates in logic Leakage power dominates in memory Small activity Dynamic: access one 32b word at a time in 32MB memory Leakage: in all other 32MB-4B mem cells Also in devices that are mostly in stand-by, e.g. cell phones Different methods must be applied Claude Schmitt, Panels discussion It's About Power - Performance and area alone don't quite cut it anymore!, DATE 2/14/2005. #13/67 Erno Salminen - Nov. 2012

Memory power dominates in small devices Figure: [Verma, N.;, "Analysis Towards Minimization of Total SRAM Energy Over Active and Idle Operating Modes," TVLSI, vol.19, no.9, pp.1695-1703, Sept. 2011].

14 Memory power dominates in small devices Figure: [Verma, N.;, "Analysis Towards Minimization of Total SRAM Energy Over Active and Idle Operating Modes," TVLSI, vol.19, no.9, pp , Sept. 2011]. Citiations: [1] J. Kwong,et al. I A 65nm subvt n IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2008, pp [2] V. Georgeet al. Penryn: 45-nm in Proc. IEEE Asian Solid-State Circuits Conf., Nov. 2007, pp #14/67 Erno Salminen - Nov. 2012

15 Power consumption in CMOS (1) Two measures Peak power consumption Average power consumption Usually more interesting than peak power However, large peaks degrade battery life-time and cause electronmigration Pavg = Pdynamic + Pshort + Pleakage i dyn i short V in V out C out i short a) Dynamic b) Short circuit c) Leakage W. Burleson, ECE 679V, course material, 2002, ure3.ppt #15/67 Erno Salminen - Nov. 2012

16 Power consumption in CMOS (2) P dynamic has been dominant in CMOS (~50-90%) Leakage power likely has increased with smaller geometries! E.g. P short + P leakage = but 65nm P dynamic = K * C out * V dd2 * f K = avg transitions on node per clock cycle C out = driven output capacitance of node V dd = supply voltage f = operating frequency HUOM! OBS! Muy importante! Faulty circuits, may have also P static E.g. there is DC from Vdd to GND, if gate of PMOS is stuck-at-zero #16/67 Erno Salminen - Nov. 2012

17 Reducing dynamic power Minimize P dynamic = K * C out * V dd2 * f Hence, minimize 1. activity K 2. the amount of logic (capacitance) Cout 3. supply voltage Vdd quadratical impact! 4. frequency f aim for just fast enough 5. combination of the above Parameters are coupled E.g. high f, requires large Vdd Parallel processing may increase C but lowers f and hopefully Vdd #17/67 Erno Salminen - Nov. 2012

18 Capacitance and switching minimization Minimize K, i.e. useless switching K depends on input sequence Disable new values from entering the logic when results are not needed C out = C fo + C w + C p C fo = input capacitances of fan-out gates (~50%) C w = wiring capacitance (~40%, increases with new technologies), hard to estimate before placement C p = parasitic capacitance of driving gate itself (~ 10%) No need to minimize C if it is rarely switched C eff = K * C out, effective capacitance C out might increase when C eff minimized in restructuring Still beneficial #18/67 Erno Salminen - Nov. 2012

Minimizing Vdd in kind of tempting Designer can rarely change the voltage freely,there are e.g. 3-4 choices, not continous scaling Decreasing V dd, increases delay of transistors (=t p ) Decreasing V dd reduces noise margin 5.

Nikolic, slide set for book Digital Integrated Circuits A Design Perspective,2002, http://bwrc.eecs.berkeley.edu/icbook/slides/chapter5.ppt ] Fig2: [A. Sasan et al.

19 Minimizing Vdd in kind of tempting Designer can rarely change the voltage freely,there are e.g. 3-4 choices, not continous scaling Decreasing V dd, increases delay of transistors (=t p ) Decreasing V dd reduces noise margin Inverter delay t p 4 t p (normalized) V (V) DD Fig1: [J.M. Rabaey, A. Chandrakasan, B. Nikolic, slide set for book Digital Integrated Circuits A Design Perspective,2002, ] Fig2: [A. Sasan et al."variation Trained Drowsy Cache (VTD-Cache): A History Trained Variation Aware Drowsy Cache for Fine Grain Voltage Scaling," TVLSIvol.20, no.4, pp , April 2012 #19/67 Erno Salminen - Nov. 2012

20 Voltage vs. Frequency vs. Power Implementing low-power configurable processors - practical options and tradeoffs, Wei, J.; Rowen, C.; Design Automation Conference, Proceedings. 42 nd,13-17 June 2005 Page(s): #20/67 Erno Salminen - Nov. 2012

21 Power vs. energy HUOM! OBS! Batteries store energy not power Power measures rate of energy consumption Muy importante! Energy E = P * t saving is often the real goal! Decreasing f, increases t Frequency scaling alone does not decrease energy Execution time t is usually constrained S. Dey, Design of Low-Power, Battery-Efficient Systems, ECE206C course material, UCSD, #21/67 Erno Salminen - Nov. 2012

22 PDP and EDP Power-Delay Product PDP = P * t avg. energy consumed per switching event Watt*sec = Joule Energy-Delay Product EDP = PDP*t avg. energy multiplied by execution time These metrics account the trade-off between increased delay and lower energy/operation Different mininum points Normalized value #22/67 Erno Salminen - Nov min Supply voltage [V] min energy*delay power*delay power delay

23 Low-power design at system level Erno Salminen - Nov. 2012

Importance of design level abstraction level Applies to all design decision not just power Level People System designers Front-end ASIC designers Back-end ASIC designers effect

24 Importance of design level abstraction level Applies to all design decision not just power Level People System designers Front-end ASIC designers Back-end ASIC designers effect Alexander Worm, Algorithm Manipulation for Low-Power Communication Circuit Implementation, Tampere SoC, Nov Who copied the figure from: #24/67 Erno Salminen - Nov. 2012

25 [ #25/67 Erno Salminen - Nov. 2012

26 More power reduction methods asd Importance in future - -/ /+ + Barry Pangrle, Panels discussion It's About Power - Performance and area alone don't quite cut it anymore!, DATE 2/14/2005. #26/67 Erno Salminen - Nov. 2012

27 System-level: Choose: the right implementation style Point solutions are of course most efficient w.r.t to power, but offer reduced flexibility Large differences: 9x-1075x! Pay attention to ratio P active /P idle Poor ratio (small) in general-purpose devices Is there any more worthless thing that burning power for doing nothing? Power consumption in various applications Device Unit MP3 Web notes messaging Ratios idle rcv reply speaker headphone browse text audio text audio max/min min/idle max/idle laptop [W] handheld [W] cellphone [mw] pager [mw] high-end MP3 [mw] low-end MP3 [mw] voide recorder [mw] ratio = laptop/min Table: [Mayo, Ranganathan, Energy consumption in mobile devices..., HPL , 2003] #27/67 Erno Salminen - Nov. 2012

5-5 MIPS/mW Flexibility 100-1000 MOPS/mW

DSP (TI C6xxx) Embedded Processor (IpArm)

28 System level: Choose the right digital architecture (1) MIPS/mW Flexibility MOPS/mW MOPS/mW Prog Mem MAC Unit mp Addr Gen DSP (TI C6xxx) Embedded Processor (IpArm) Embedded FPGA Reconfigurable Processors (Maia) Factor of Direct Mapped hardware Power Dissipation Gary Kelson, BWRC Overview, June #28/67 Erno Salminen - Nov. 2012

29 System level: Choose the right digital architecture (2) [Jan Rabaey, System-on-a-chip: A case for heterogeneous architecture, Tampere Soc, 1999]. #29/67 Erno Salminen - Nov. 2012

30 Will new technologies minimize heat? What next? [H. Harrer, G.A. Katopis, G.A.; Becker, W., From chips to systems via packaging - A comparison of IBM's mainframe servers, IEEE circuits and systems, Vol. 6, Iss. 4, 2006, pp ] #30/67 Erno Salminen - Nov. 2012

31 Methods for dynamic power management Erno Salminen - Nov. 2012

32 Dynamic power managements (DPM) Configures electronic systems at run-time to provide required performance with minimal activity Applicable if components experience non-uniform workload Predictable periods of activity and idleness e.g. simple timeout policy in laptops shuts down components if they have been idle for certain period Power manageable component (PMC) has two or more modes of operation a) High performance and power consumption b) Low performance and power Usually the number of modes very limited to handful #32/67 Erno Salminen - Nov. 2012

Full speed is not required all the time Running at full speed wastes energy The workload is NOT constant But hard to forecast at design-time Adapt

33 Full speed is not required all the time Running at full speed wastes energy The workload is NOT constant But hard to forecast at design-time Adapt dynamically [L.A. Barroso, U. Holzle, The Case for Energy-Proportional Computing, Computer, Vol. 40, Iss. 12, 2007, pp ] #33/67 Erno Salminen - Nov. 2012

is far from ideal Energy seems to be way too cheap

34 Full speed power is not required all the time (2) Current servers do use dynamic management Efficiency is far from ideal Energy seems to be way too cheap Wasted power Ideal power #34/67 Erno Salminen - Nov. 2012

35 Power control unit Determines when FU is shut down Rule of thumb: pow_ctrl area < 1/10*FU area Power consumption of power control must be smaller than resulting savings Either shut down the Clk and/or V dd State is lost, if V dd shut down Shutdown and recovery have nonnegligible delays Shutting down is not beneficial if sleep state is short Hard to determine to optimal timing Performance loss due to recovery time Power ctrl a) Power supply shut-down Power ctrl latch clk_disable Clk b) Clock gating principle #35/67 Erno Salminen - Nov. 2012

36 Power supply shutdown Cut of power supply with switch Removes also P leakage Switch has non-ideal delay T and resistance R Physical placement and layout important due to transient noise Volatile memories (RAM, flip-flops) lose their state Must be saved elsewhere and restored Longer shutdown/wakeup delays Utilized in coarse-grain not with small units inside the chip #36/67 Erno Salminen - Nov. 2012

37 Isolating the shutdown units Isolate the sleeping unit from its neighbors Drive control and status signals into inactive state E.g. sleeping FIFO appears full and other won t try to write data to it At the same time, sleeping FIFO appears empty and other cannot read from it Sometimes all ouput signals must be frozen during sleep (even if power is cut) active isolation ring active PRODUCER full data FIFO 1 (sleeping) 0 data valid CONSUMER we re Vdd enable= 0 power ctrl #37/67 Erno Salminen - Nov. 2012

Power supply shutdown example as http://failblog.files.wordpress.

38 Power supply shutdown example as #38/67 Erno Salminen - Nov. 2012

39 Clock gating Clock of FU is shut down Needs latch and AND gate to avoid glitches Adds clock skew Input values do not propagate through input registers No switching inside FU Relatively simple and low overhead control Automatic clock gating supported in CAD tools Small grained control, even at the level of a couple of DFF s #39/67 Erno Salminen - Nov. 2012

40 Clock gating (2) Well suited for self-managed components Clock distribution network itself consumes energy Highly active (K=1) Large net = large capacitance Stop master clock PLL or oscillator However, most energy consumed by local clocks GALS approach may help since large global clock network may be splitted into several small clock networks #40/67 Erno Salminen - Nov. 2012

$Clock tree power 30% of the total power is attributed to clock in Pentium Most of the clock power is used in the final clock buffers and flip-flops Larger fraction in clock tree itself in (mobile)$

41 Clock tree power 30% of the total power is attributed to clock in Pentium Most of the clock power is used in the final clock buffers and flip-flops Larger fraction in clock tree itself in (mobile) SoCs with P_tot around few Watts Long clk wires, lots of clk buffers, low-power logic Try to gate the clock as high as possbile Cluster the logic blocks together depending how their clk is gated Self-managed low-level clk gating happens here Power breakdown in Pentium: Explcit system-level clk gating happens here and shuts down larger fraction of the chip S. Rusu, Tampere Soc 2004 who copied this from So called H-tree clock distribution. Clock skew is balanced with matched wire lengths and multiple buffers #41/67 Erno Salminen - Nov. 2012

42 Reducing clock network power as high as possible in clk tree S. Rusu, Tampere Soc In GALS, all local clocks can be optimized separately #42/67 Erno Salminen - Nov. 2012

43 Orig DFS =f/2 Dynamic Frequency/Voltage-Freq Scaling (DFS / DVFS) DFS : frequency is changed at runtime DVFS : both frequency and voltage are changed at runtime Computation takes only 8 cycles and deadline in 16 cycles It seems that DFS brings not benefit E(orig) =t * P E(DFS)= 2t * P/2 = E(orig) DVFS =f/2 =0.71*Vdd time E(DVFS) = 2t * P/4 = E(orig)/2 #43/67 Erno Salminen - Nov. 2012

44 DFS/DVFS: Idle power is not zero! Total energy = active + idle energy Idling takes power also, especially in CPUs However, idle period might be too short for sleeping Lower frequency reduces idle period after computation lower energy also with DFS P(idle) > 0 W P (act) P (idle) Cycle time # Cycles (act) # Cycles (idle) Energy (act) Energy (idle) Energy (tot) Saving % Orig DFS DVS #44/67 Erno Salminen - Nov. 2012

45 Logic islands Large chip is divided into so called islands or domains They are regions where all the logic has something in similar Three basic island types 1. Same clock source and control (dozens such islands in a complex SoC) 2. Same power gating control (~dozen) 3. Same supply voltage (handful) E.g. I/O 3.3V, CPU 1.1V, on-chip mem. 1V Domain crossing always needs special care! #45/67 Erno Salminen - Nov. 2012

46 Controlling DPM Erno Salminen - Nov. 2012

47 Power-managed systems Observer collects workload information Controller forces transitions between power states Centralized control is prblematic in large systems Some units are self-managed and some need a system-level controller #47/67 Erno Salminen - Nov. 2012

48 Power state machine (PSM) PSM models the possible operating states of a SoC as well as the costs of transitions and states Designers use it to analyze the operation and to design the policy for power management Low power states have lower performance longer transition latency #48/67 Erno Salminen - Nov. 2012

49 Power state machine (2) Strong ARM SA-1100 (cf. fig 1) can be modeled with FSM below Transition RUN IDLE is so fast that Greedy policy applicable they can be combined into single state ON (selfmanaged with greedy policy) P ON is weighted sum of P RUN adn P IDLE OFF coresponds to state Sleep #49/67 Erno Salminen - Nov. 2012

50 Controlling power state transitions Trivial greedy policy can be used, if transitions are instantaneous and consume no power Not realistic assumption Returning from power-down mode requires 1. turning on and stabilizing power supply 2. reinitializing system 3. restoring context non-negligible delay and energy Tolerated performance degradation must be explicitly stated, e.g. no more than 5% Max power saving when device is not designed at all. However, performance loss is 100%... #50/67 Erno Salminen - Nov. 2012

51 Break-even time (1) No computation possible during state transition performance loss Break-even time T BE for inactive state is the minimum inactivity time required to compensate the cost of state transition(s) Cost depends on transition times and power comsumption(s) If inactive time T n < T BE, it is not beneficial to enter inactive state because cost is not compensated #51/67 Erno Salminen - Nov. 2012

52 Break-even time (2) In simple case, T BE is sum of time for entering state and exiting state Assuming that state transition does not increase power consumption (like it does with hard-drives) Multiple power states result in multiple breakeven time values #52/67 Erno Salminen - Nov. 2012

53 Applicability of DPM One can calculate the max power saving P saved,max = P on P ideal where P ideal refers to P with ideal DPM States with small T BE are more likely applicable, e.g. Strong-ARM T BE,idle = 0.02 ms T BE,sleep = ms Idle state can be entered much more often Workload T BE,idle / 2 Power with Idle Power with Sleep Time Fig. Example of ideal DPM policy (workload known a priori, and hence wakeups always on time and no performance loss) #53/67 Erno Salminen - Nov. 2012

54 Applicability of DPM (2) Workload In most cases, workload is not known a priori and DPM reacts to the changes Sometimes, workload is known, e.g. sampling sensor values once per second and processing them Power with Idle, ideal DPM Power with Idle, real DPM Entering idle state gets delayed until utilization drops below threshold Start waking up when computation is needed. Processing gets delayed Fig. Difference between ideal and realistic DPM policies #54/67 Erno Salminen - Nov. 2012

55 Prediction In real world, little information (or not at all) is availbale about future inputs Must predict Overprediction/Underprediction Predicted idle period longer/shorter than actually Overprediction causes performance loss Not enough time for wakeup Underprediction consumes unnecessary power Low power mode not entered always #55/67 Erno Salminen - Nov. 2012

56 Prediction methods a) Fixed timeout : When elapsed idle time longer than threshold, enter low-power mode Big threshold increases performance and power Waste power when waiting for timeout Performance loss upon wakeup b) Predictive shutdown Predict idle time from duration past idle and active periods No automatic way to decide regression equation Offline data collection required Predict idle time from last active period Short active periods are usually followed by long idle periods Offline data required #56/67 Erno Salminen - Nov. 2012

57 Prediction methods (2) c) Predictive wakeup To reduce performance loss When elapsed time in low-power mode longer than threshold, start wakeup procedure Increases power in idle period longer than predicted d) Adaptive methods change threshold at runtime E.g. use several timeout values and measure how well they perform #57/67 Erno Salminen - Nov. 2012

58 Selecting T BE in fixed timeout Psaved (mw) Interactive programs (e.g. games) have shorter idle periods With high breakeven time, lowpower mode seldom used Plot of P (T ) for the Sleep state of the StrongARM SA-1100 processor. The three curves refer to three different workload statistics, computed from real-world CPU traces provided by the IPM monitoring package [5]. #58/67 Erno Salminen - Nov. 2012

59 Safety vs efficiency Safety means probability of avoiding performance loss there s always some loss Efficiency means proportion of achieved power saving from ideal saving Quality of a timeout-based predictor evaluated as a function of timer duration. Safety and efficiency of the timeout used to predict idle periods longer than T=160 ms. #59/67 Erno Salminen - Nov. 2012

60 Predictive shutdown Example threshold (i.e active periods shorter than this are likely followed by long idle time) Next L-shape is necessary condition for prediction Fig. 7. (a) Scatter plot of T versus T for the workload of the CPU of a personal computer running Linux. #60/67 Erno Salminen - Nov. 2012

61 Conclusion Power saving does not necessarily save energy Basic methods Low-power technology, signal reordering Minor effect, not interesting Voltage scaling, power shutdown Diffcult, voltage levels CANNOT be freely chosen Frequency scaling Must not sacrifice performance too much Does not affect energy/task, if used alone Clock gating, enabled flip-flops Reasonable way for energy saving Supported by CAD tools #61/67 Erno Salminen - Nov. 2012

62 Conclusion (2) Several power/performance modes needed Modes have different break-even times Policy defines the current operating mode Static Adaptive Policy decisions based on off-line data monitoring #62/67 Erno Salminen - Nov. 2012

63 Extra Erno Salminen - Nov. 2012

64 Power breakdown: Imagine stream processing chip Smart memory hierarchy: memories ~21% Mattan Erez, Stream Architectures Programmability and Efficiency, Tampere SoC, Nov #64/67 Erno Salminen - Nov. 2012

65 Reminder: opt for locality compare Mattan Erez, Stream Architectures Programmability and Efficiency, Tampere SoC, Nov #65/67 Erno Salminen - Nov. 2012

66 Glitch Minimization Low-level technique Glitches may add 20% to power [Raghunathan, DAC96] Raghunathan et al. suggest RTL modifications to decrease glitches Stop glitch propagation (e.g. with registers) Glitch generation (due to uneven gate delays) not considered Important to avoid glitches in control signals #66/67 Erno Salminen - Nov. 2012

67 Power reduction methods Implementing low-power configurable processors - practical options and tradeoffs, Wei, J.; Rowen, C.; Design Automation Conference, Proceedings. 42 nd,13-17 June 2005 Page(s): #67/67 Erno Salminen - Nov. 2012

68 Shutting down units Functional unit (FU) Unit is idle when its output values are not needed Hence, it can be shut-down a) External idleness changes in units output are not visible in system outputs Ouput of ADD is don t care ADD doesn t know that by itself b) Internal idleness units output do not change even if units inputs change State-holding required Not practical to detect all idle conditions Too large overhead Detect most common ADD SUB 1 or 2 a) ADD is externally idle Functional unit (FU) ADD SUB #68/67 Erno Salminen - Nov b) FU is internally idle

69 #69/67 Erno Salminen - Nov. 2012

70 Stochastic methods Take into account uncertainty in workload, power consumption, and reponse times many power states, buffers, queues etc. Offer contolled trade-off between performance and power Controlled Markov chains Service requester (SR) models workload Service provider (SP) model power modes Power manager implements commands for SP Cost metrics combines power and performance #70/67 Erno Salminen - Nov. 2012

71 Stochastic methods (2) State transitions have probabilities Bursty workload in Fig 9a) 0= no request/workload 1= request issued High probability (0.85) for several requests in a row Average request stream 1/(1-0.85) = 6.7 requests SR = workload SP = power modes #71/67 Erno Salminen - Nov. 2012

72 Stochastic methods (3) Power mode is changed with commands switch_on and switch_off Transition probabilities model the transition delay Even if switch_off is issued, transition does not occur immediately Advantages Possible to search global optimum Exact solution in polynomial time Strength and optimality of randomized policies Note Performance and power are expected values, no guarantees given Hard to obtain accurate Markov models #72/67 Erno Salminen - Nov. 2012

73 ACPI Advanced Configuration and Power Interface by Intel, Microsoft and Toshiba Defines interfaces between OS and HW Targets personal computers (PCs) #73/67 Erno Salminen - Nov. 2012

74 ACPI (2) Max wakeup time System has 4 global power states G0 = ON, G3=OFF Additional state legacy if devices don n support ACPI State G1 (sleeping) divided into 4 sub-states State G0 (ON) divided into 4 device states and 4 processor states OFF Min wakeup time ON #74/67 Erno Salminen - Nov. 2012

75 Case: ACPI with hard disk Power management SW takes <1% of time Wakeup power (52.5J / 7s) is larger than active power Due to inertia when disks start rotating Break-even time 17.6 sec Power reduction 23-55% active idle, disks rotating OFF #75/67 Erno Salminen - Nov. 2012

76 Case: Results T break-even sec #76/67 Erno Salminen - Nov. 2012

Department of Computer Systems. Remember the guest lecture+conclusions Wed in TB219 starting at 10:15

Department of Computer Systems. Remember the guest lecture+conclusions Wed in TB219 starting at 10:15 TKT-2431 Soc Design Lec 11 Energy consumption Erno Salminen Tampere University of Technology Fall 2011 Remember the guest lecture+conclusions Wed 23.11.2010 in TB219 starting at 10:15 Erno Salminen - Nov.