Reconfigurable Computing Lab 01: Traffic Light Controller

Transcription

1 Informatik 12 Cauerstr Erlangen Reconfigurable Computing Lab 01: Traffic Light Controller In this lab, a traffic light controller (see Exercise 1) will be implemented on the Digilent Spartan-3 Starter Kit board (XC3S200-FT256-4). mclk reset pedestrian_ns pedestrian_ew cars_ns cars_ew TLC_VISUAL red green blue Horiz_sync_out Vert_sync_out Figure 1: Entity tlc visual A VHDL design to visualize the behaviour of the controller will be provided. The module TLC_VISUAL will display the intersection and traffic lights on a connected display (ensure that a monitor is connected to the board by using the VGA interface). The interface to this module is shown in Figure 1. Here is a description of the interface signals: mclk: is the main clock of the board (50MHz = 20ns). reset: is the reset signal and it is mapped to Btn3 of the board. pedestrian ns: can take one of the two values TLF_RED or TLF_GREEN that are predefined constants. If the value is TLF_RED the pedestrians may not cross the intersection in north-south direction. Pedestrians may cross the intersection if pedestrian ns is set to TLF_GREEN. pedestrian ew: like pedestrian ns, this signal controls the pedestrian crossings in east-west direction. In both pedestrian ns and pedestrian ew cases, Btn1 has to be pressed for 1second to enable pedestrians to cross the intersection. cars ns: analogous to pedestrian ns this signal can be equal to TLC_RED or TLC_GREEN and controls whether cars may cross the intersection in north-south direction. cars ew: this signal control whether cars may cross the intersection in east-west direction. 1

2 mclk reset CLK_DIV: process iclk???: process mclk reset pedestrian_ns pedestrian_ew cars_ns cars_ew LED TLC_VISUAL red green blue Horiz_sync_out Vert_sync_out LED traffic_light_top Figure 2: Overview over traffic light top.vhd Laboratory In this lab, you shall complete the file TRAFFIC_LIGHT_TOP.VHD by providing the connection to module TLC_VISUAL (see Fig. 2). You also need to implement a finite state machine (according to Fig. 3) for the traffic light controller. Please, note that all sources files are available at /scratch-local/rc/lab01/. The states of your FSM are described as follows: 1. S0: 2. S1: 3. S2: 4. S3: cars ns: TLC_RED cars ew: TLC_GREEN pedestrian ns: TLF_RED pedestrian ew: TLF_RED cars ns: TLC_GREEN cars ew: TLC_RED pedestrian ns: TLF_RED pedestrian ew: TLF_RED cars ns: TLC_RED cars ew: TLC_RED pedestrian ns: TLF_GREEN pedestrian ew: TLF_GREEN 2

3 cars ns: TLC_RED cars ew: TLC_RED pedestrian ns: TLF_GREEN pedestrian ew: TLF_GREEN Btn(1)=1 S2 S0 S3 Btn(1)=0 Btn(1)=0 S1 Btn(1)=1 Figure 3: Finite state machine for the traffic light controller Steps 1. Opening a Xilinx ISE (Integrated Synthesis Environment) Project: Change from your home directory: cd /scratch-local/rc/lab01/ Load the Xilinx ISE Design Suite: module load ise/13.4_x86_64-pc-linux Start the tool and let it running in background: ise& Open the given ISE project lab01.xise. Fig. 4 presents the Xilinx ISE project navigator 2. Based on Fig. 2 and Fig. 3, complete the file TRAFFIC_LIGHT_TOP.VHD. 3. Test the functionality of your design by simulating it with Questa Sim. Load the simulation tool with the command: module load modelsim/10.2c_x86_64-pc-linux Start simulation: vsim& Create a new project and specify lab01 as project name Add all.vhd files from the folder hdl As depicted in Fig 5, compile all files by selecting the options Compile Order and Auto Generate Start the simulation and select the module tb_traffic_light_top from the library work Add all signals from inst_dut to visualize their wave forms Run your simulation. Fig. 6 shows the expected simulation result 3

4 Figure 4: Xilinx ISE project navigator Figure 5: Compilation process using Questa Sim 4

5 Figure 6: Simulation process with Questa Sim 4. Once you validate your design with Modelsim, switch to ISE and generate the bitstream and load it on the FPGA. 5. Test your design on the Digilent Spartan-3 Starter Kit board. First, you have to start the program impact on a terminal. 6. Select the device xc3s200, then, assign a new configuration file and program it (see Fig. 7). 7. Using a VGA cable, connect the board to a display and check the results. 8. Additional Tasks (optional): Increase the time of all green signals to 5 seconds Decrease to 2 seconds the time of the green signal for pedestrians 5

6 Figure 7: Assigning a configuration file and programming an FPGA with Xilinx Impact 6