IBIS 在信号完整性分析中的应用 Using IBIS for SI Analysis
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1 IBIS 在信号完整性分析中的应用 Using IBIS for SI Analysis Lance Wang, ZhangMin Zhong Cadence Design Systems, Inc. Asian IBIS Summit, Shen Zhen, P.R. China December 6, Copyright 2005, Cadence Design Systems Inc.
2 Outline What happened on IBIS (IBIS 历史 ) Why IBIS (IBIS 的好处 ) Speed and Accuracy ( 速度和精度 ) Industrial Examples ( 工业化例子 ) Advanced IBIS Technologies ( 加强型 IBIS 技术 ) Complex-IO Devices ( 复杂 I/O 器件 ) Macromodeling is a solution ( 宏模型解决方案 ) Experiences and Industrial Examples ( 经验和工业化例子 ) 2 Copyright 2005, Cadence Design Systems Inc.
3 Outline What happened on IBIS (IBIS 历史 ) Why IBIS Speed and Accuracy Industrial Examples Advanced IBIS Technologies Complex-IO Devices Macromodeling is a solution Experiences and Industrial Examples 3 Copyright 2005, Cadence Design Systems Inc.
4 What happened on IBIS - Spice Transistor Level Models 晶体管级模型建模流程 Model Layout Extractions 非选择性提取 -Very Complicated -A lots of unusable stuff -Too slow in the simulations 4 Copyright 2005, Cadence Design Systems Inc.
5 What happened on IBIS - Behavioral Models 行为级模型建模流程 Data Data Data Data Behavioral Extractions 选择性提取 5 Copyright 2005, Cadence Design Systems Inc. Model
6 What happened on IBIS - IBIS is behavioral Model (IBIS 是行为级模型 ) 6 Copyright 2005, Cadence Design Systems Inc.
7 What happened on IBIS - The Original Box 1 st PCI Chipset (33 MHz) IBIS 1 st Pentium up (66 MHz) 7 Copyright 2005, Cadence Design Systems Inc.
8 and the Box did grow 1 st PCI Chipset (33 MHz) IBIS 1 st Pentium up (66 MHz) An increasing amount of Complex IO models are missing the box 8 Copyright 2005, Cadence Design Systems Inc.
9 What happened on IBIS - IBIS Model Vendors(IBIS 模型提供者 ) 120.0% Top10 IBIS Model Vendors on Web 100.0% 120.0% 100.0% 80.0% 60.0% 40.0% 20.0% 0.0% 80.0% 60.0% Total actalyst Elpida (10) infineon Intel (1) Motorola (4) NEC On Semi (9) Pericom Semi (6) Philips Semi (2) Basic IO Series S-switch Diffpair model selector Pin Paractic PackageModel default pin parasitic Pin Paractic EBD# Other(dynamic C, driver S) default pin parasitic EBD# Other(dynamic C, driver S) 40.0% 20.0% 0.0% Total Actel (7) Elpida (10) IDT (5) Intel (1) Motorola (4) National Semi (8) On Semi (9) Pericom Semi (6) Philips Semi (2) TI (3) Basic IO Series S-switch Diffpair model selector PackageModel 9 Copyright 2005, Cadence Design Systems Inc.
10 What happened on IBIS - IBIS in EDA Tools(IBIS 在 EDA 工具中的应用 ) Major EDA Simulators are supporting IBIS now Cadence Mentor SPICE Simulators are taking IBIS now!!! SPICE Synopsys Simulators are taking Zuken Agilent And many, many more 10 Copyright 2005, Cadence Design Systems Inc.
11 Outline What happened on IBIS Why IBIS (IBIS 的好处 ) Speed and Accuracy ( 速度和精度 ) Industrial Examples ( 工业化例子 ) Advanced IBIS Technologies Complex-IO Devices Macromodeling is a solution Experiences and Industrial Examples 11 Copyright 2005, Cadence Design Systems Inc.
12 Why IBIS (IBIS 的好处 ) -Speed and Accuracy ( 速度和精度 ) Behavioral data in Spice simulators I(pad) = Ipd(V(pad)-V(gnd))*Wd(t) + Icd(V(pad)-V(gnd_c)) + Ipu(V(pad)-V(pwr))*Wu(t) + Icu(V(pad)-V(pwr_c)) Results are accurate Much, much faster simulation time times faster IP Protected HSpice Transistor Model vs. IBIS Model 12 Copyright 2005, Cadence Design Systems Inc.
13 Why IBIS (IBIS 的好处 ) - Industrial Examples( 工业化例子 ) (133MHz) Driver: IDT 79RC32438 Receiver: Micron MT46V16M8TG Blue: Measured result Red: Simulated result 13 Copyright 2005, Cadence Design Systems Inc.
14 Why IBIS (IBIS 的好处 ) - Industrial Examples( 工业化例子 )(622Mbps) CON CON PCB1 BACKPLANE PCB2 TDCS6440G VSC Copyright 2005, Cadence Design Systems Inc.
15 Why IBIS (IBIS 的好处 ) - Industrial Examples( 工业化例子 )(622Mbps) Eye Height: 210mv Eye Width: 1.1ns Eye Height: about 240mv Eye Width: about 1.15ns 15 Copyright 2005, Cadence Design Systems Inc.
16 Outline What happened on IBIS Why IBIS Speed and Accuracy Industrial Examples Advanced IBIS Technologies( 加强型 IBIS 技术 ) Complex-IO Devices ( 复杂 I/O 器件 ) Macromodeling is a solution ( 宏模型解决方案 ) Experiences and Industrial Examples ( 经验和工业化例子 ) 16 Copyright 2005, Cadence Design Systems Inc.
17 Complex-IO Devices( 复杂 I/O 器件 ) Pre-emphasis 预加重 /De-emphasis 去加 Emphasis (t) = Input (t-1) Main (+ & -) Input stimulus pattern TX+ Pad TX- Pad Emphasis stimulus pattern X X in concert in opposition Boost (+ & -) Picture from Michael Mirmak s presentation in DesignCon East IBIS Summit Copyright 2005, Cadence Design Systems Inc.
18 Complex-IO Devices( 复杂 I/O 器件 ) 18 Copyright 2005, Cadence Design Systems Inc.
19 What is MacroModeling and Why? KEY Methodology only 19 Copyright 2005, Cadence Design Systems Inc.
20 Macromodel from architecture templates 从器件结构中得出宏模型 Most modern devices are based on known DSP circuit architectures Serial-to- Parallel Clock Recovery Unit Pattern Detector & Word Aligner Recovered Clock to Core Rate Matcher & Channel Aligner 8B/10B Decoder Match template parameters to Layout model to get an accurate macromodel Rt Vtt out Reference Clock Rx PLL Reference Clock Transceiver PLL in UI dly 8B/10B Encoder Known circuit architecture Parallelto-Serial Synchronizer Synchronizer Macromodel template with parameters 20 Copyright 2005, Cadence Design Systems Inc.
21 Industry example- Altera Stratix GX Altera successfully adapted the MacroModel templates to produce fast and accurate models of our multi-gigabit transceivers. Not only did the resulting model correlate well, it also simulates between 20 to 400 times faster than its transistor-level counterpart. And the model can be easily adjusted to match the behaviors of actual silicon measured in the lab. Correlation: MacroModel vs TransistorModel Overall, the templates were simple to work with and very valuable amidst the challenges of multi-gigahertz design." 21 Copyright 2005, Cadence Design Systems Inc.
22 Correlation - Altera Stratix GX - Transistor Level Model (HSpice) - Spice Macromodel (Cadence DML) Transmitter output at factor=0 factor=1 factor=2 factor=3 factor=4 factor=5 22 Copyright 2005, Cadence Design Systems Inc.
23 Case Study: Agere Systems 4 Gbps SerDes Given transistor simulation output and macromodel template, how many iterations and how much time required to make an accurate model? Final Correlation 17 th Iteration 54 minutes ~400x faster sim Adjusted 1. rt 2. scale 3. cf1 4. padcap 5. dt 6. c_comp 23 Copyright 2005, Cadence Design Systems Inc.
24 Cadence IBIS 4.1 Kit IBIS IBIS Kit Kit README IBIS IBIS MODELS MODELS For For Simulators Simulators SPICE HSpice Spectre 24 Copyright 2005, Cadence Design Systems Inc. IBIS IBIS SIMULATIONS SIMULATIONS Templates Templates SerDes Gate Modulation PCI Express IO Non-ideal Power Pass-thru Rx Self-calibrating Tx DFE IBIS IBIS TOOLS Ibis2signoise Ibischk4 SPICE manual
25 25 Copyright 2005, Cadence Design Systems Inc.
New IBIS Techniques for Modeling Complex IO Cadence Webinar March 23, 2005 Donald Telian
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